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PEB1757E Datasheet(PDF) 3 Page - Infineon Technologies AG

Part No. PEB1757E
Description  Semiconductor Solutions for High Speed Communication and Fiber Optic Applications
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB1757E Datasheet(HTML) 3 Page - Infineon Technologies AG

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Published by Infineon Technologies AG
Tethys™ 4192 can process any legal mix of flexible concate-
nated signals ranging from STS-1, STS-2c, STS-3c … up to
STS-192c. Each set of concatenated signals must fit inside an
STS-48 or STS-192 boundary (depending on whether the
pointer processor is configured as an STS-48 or STS-192
block) and must be formatted as an STS-Nc frame as defined
in GR-253-CORE.
Tethys™ 4192 provides the ability for certain frame structures
to be automatically detected and configured into the device.
This feature allows the user to interface to systems with
unknown standard payload concatenation configurations.
Various diagnostic features are provided. Framed PRBS-32
can be generated and checked on any channel via loop backs.
Errors can be inserted into B1, B2, H1 and H2 bytes on a bit-
by-bit basis.
To support asynchronous timing between different physical
ports, Tethys™ 4192 provides STS-1 level pointer processing
for quad STS-192 interfaces in the receive direction. On the
line side receive interface, all inputs can be asynchronous with
frequency differences of
± 20 ppm.
The pointer processor on the receive side adjusts for these dif-
ferences and outputs the STS-192 or STS-48 streams based
on the line timed or system frequencies selected on the sys-
tem side. In the transmit direction, the system side ingress
ports and line side egress ports must be locked to the same
Tethys™ 4192 aggregates all STS-48 or STS-192 ports from
the system side to the line side in the transmit/multiplex direc-
tion. In the case of quad STS-192 interfaces on the line side,
any one of the STS-48 ports can be aggregated into any one
of the STS-192 line side ports.
To select the best timing available in the system, the S1 bytes
are processed and the system has the option to select either
timing from the line or timing from the local reference source.
On the system side, the receive outputs can be line timed to
their respective system side transmit inputs.
When interfacing the system side physical ports to different
transmission paths, the ports can have skew of up to
± 250 ns.
This skew must be tolerated in order to support the normal
multiplex of STS-48 streams to higher rate signals to the line
side. For this purpose, Tethys™ 4192 includes de skew buffers
for desks of up to
± 250 ns between the ports on the system
Tethys™ 4192 generates and detects all SONET/SDH rele-
vant alarms and defects, including LOS, LOF, RDI-L, REI-L,
AIS-P, AIS-L and LOC on each line side and system side inter-
Tethys™ 4192 is a highly integrated device that implements
full duplex SONET/SDH processing at STS-192/STM-64 or
STS-48/STM-16 rates. In the rest of this document, only
SONET terminology will be stated. However, SDH terminology
applies equally well unless otherwise written.
Tethys™ 4192 supports up to 40 Gbit/s bandwidth or 80 Gbit/s
full-duplex. It provides section, line, and path overhead pro-
cessing and supports framing, scrambling/de scrambling,
alarm signal insertion/detection, bit interleaved parity
(B1/B2/B3) processing, path overhead processing, pointer pro-
cessing and TOH and POH transparency. It also provides sub-
stantial performance monitoring of TOH/POH overhead for the
receive direction with 1 second count accumulation.
On the line side, quad STS-192 are supported. The interface
utilizes SFI-4.2 or SFI-4.1. The STS-192 interfaces can be
received at differing clock frequencies, depending on the
SONET line clock variation of
± 20 ppm. Similarly, the STS-192
outputs can be line timed to the corresponding incoming
On the system/client side, quad STS-192 or sixteen STS-48
can be interfaced. In this case, a 4
× 2.5 Gbit/s or serial
2.5 Gbit/s is utilized for the respective interfaces.
The System side can support 16 independent STS-48 links or
four groups of STS-192 links, where each group of an
STS-192 link consists of four 2.488 Gbit/s links. This means for
instance that 8 STS-48’s and two STS-192’s can be supported
at the same time. Or alternatively, three STS-192’s and four
STS-48’s. In fact, any legal mix of interfaces can be supported.
The selection/configuration of the system and line side inter-
faces is completely independent.
All TOH (A1 … E2) bytes can be added/dropped onto the par-
allel TOH/POH interfaces. This applies in both receive and
transmit directions.
All POH passing through the device can be added or dropped
onto the TOH/POH ports. The TOH and POH ports are physi-
cally shared.
Detected alarms like LOS, LOF, SEF, AIS-L can be dropped
onto the parallel Alarm Drop Interfaces. This applies in both
the receive and transmit directions. In addition, Tethys™ 4192
can drop the payload concatenation configuration onto the
same interface.
In TOH Transparency mode, J0, B1, E1, F1, K1, K2, D1-D12,
S1, M0/M1 and E2 bytes are transparent through the device.
In POH Transparency mode, all POH bytes, including the B3
bytes, are transparent as is. TOH/POH transparency can be
implemented through the TOH/POH ADD/DROP ports using
the dropped overhead and bit error masks on these interfaces.
This applies to both the receive and transmit directions.

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