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PEB1756E Datasheet(PDF) 3 Page - Infineon Technologies AG

Part No. PEB1756E
Description  Semiconductor Solutions for High Speed Communication and Fiber Optic Applications
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB1756E Datasheet(HTML) 3 Page - Infineon Technologies AG

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Published by Infineon Technologies AG
Tethys™ 448 can process any legal mix of flexible concate-
nated signals ranging from STS-1, STS-2c, STS-3c … up to
STS-48c. Each set of concatenated signals must fit inside an
STS-3, STS-12 or STS-48 boundary (depending on whether
the pointer processor is configured as an STS-3, STS-12 or
STS-48) and must be formatted as an STS-Nc frame as
defined in GR-253-CORE.
Tethys™ 448 provides the ability for certain frame structures to
be automatically detected and configured into the device. This
feature allows the user to interface to systems with unknown
standard payload concatenation configurations.
Various diagnostic features are provided. Framed PRBS-32
can be generated and checked on any channel via loopbacks.
Errors can be inserted into B1, B2, H1 and H2 bytes on a bit-
by-bit basis.
To support asynchronous timing between different physical
ports, Tethys™ 448 provides STS-1 level pointer processing
for sixteen STS-48 or a mix of sixteen STS-12 and STS-3
interfaces in the receive direction. On the line side receive
interface, all inputs can be asynchronous with frequency differ-
ences of
± 20 ppm.
The pointer processor on the receive side adjusts for these dif-
ferences and outputs the STS-48, STS-12 or STS-3 streams
based on the line timed or system frequencies selected on the
system side. In the transmit direction, the system side ingress
ports and line side egress ports must be locked to the same
Tethys™ 448 aggregates all STS-48 ports from the system
side to the line side in the transmit/multiplex direction. STS-3
and STS-12 rate streams received from the line side are
always multiplexed into the STS-48 rate streams on the sys-
tem side. In the receive direction, the de-aggregation of physi-
cal ports is the reverse of the transmit direction aggregation.
To select the best timing available in the system, the S1 bytes
are processed and the system has the option to select either
timing from the line or timing from the local reference source.
On the system side, the receive outputs can be line timed to
their respective system side transmit inputs.
Tethys™ 448 generates and detects all SONET/SDH relevant
alarms and defects, including LOS, LOF, RDI-L, REI-L, AIS-P,
AIS-L and LOC on each line side and system side interface
Tethys™ 448 is a highly integrated device that implements full
duplex SONET/SDH processing at STS-48/STM-16, STS-12/
STM-4 or STS-3/ STM-1 rates. In the rest of this document,
only SONET terminology will be stated. However, SDH termi-
nology applies equally well unless otherwise written.
Tethys™ 448 supports up to 40 Gbit/s bandwidth or 80 Gbit/s
full-duplex. It provides section, line, and path overhead pro-
cessing and supports framing, scrambling/de scrambling,
alarm signal insertion/detection, bit interleaved parity
(B1/B2/B3) processing, path overhead processing, pointer pro-
cessing and TOH and POH transparency. It also provides sub-
stantial performance monitoring of TOH/POH overhead for
receive direction with 1 second count accumulation.
On the line side, sixteen STS-48’s, or a mix of sixteen
STS-12’s and STS-3’s are supported. The interface utilizes
serial independent 2.5 Gbit/s links, serial independent
622 Mbit/s links or serial independent 155 Mbit/s respectively
for each interface. The STS-48, STS-12 and STS-3 interfaces
can be received at differing clock frequencies, depending on
the SONET line clock variation of ± 20 ppm. Similarly, the
STS-48, STS-12 or STS-3 outputs can be line timed to the
STS-48 inputs.
On the system/client side, sixteen STS-48 can be interfaced.
In this case, serial 2.5 Gbit/s is utilized for the respective inter-
The System side can support 16 independent STS-48 links.
The selection/configuration of the system and line side inter-
faces is completely independent.
All TOH (A1… E2) bytes can be added/dropped onto the paral-
lel TOH/POH interfaces. This applies in both receive and
transmit directions.
All POH passing through the device can be added or dropped
onto the TOH/POH ports. The TOH and POH ports are physi-
cally shared.
Detected alarms like LOS, LOF, SEF, AIS-L can be dropped
onto the parallel Alarm Drop Interfaces. This applies in both
the receive and transmit directions. In addition, Tethys™ 448
can drop the payload concatenation configuration onto the
same interface.
In TOH Transparency mode, J0, B1, E1, F1, K1, K2, D1-D12,
S1, M0/M1 and E2 bytes are transparent through the device.
In POH Transparency mode, all POH bytes, including the B3
bytes, are transparent as is. TOH/POH transparency can be
implemented through the TOH/POH ADD/DROP ports using
the dropped overhead and bit error masks on these interfaces.
This applies to both the receive and transmit directions.

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