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PEB1755E Datasheet(PDF) 1 Page - Infineon Technologies AG

Part No. PEB1755E
Description  Semiconductor Solutions for High Speed Communication and Fiber Optic Applications
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Maker  INFINEON [Infineon Technologies AG]
Homepage  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB1755E Datasheet(HTML) 1 Page - Infineon Technologies AG

  PEB1755E Datasheet HTML 1Page - Infineon Technologies AG PEB1755E Datasheet HTML 2Page - Infineon Technologies AG  
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Frea™ PEB1755E
RPR on STS-192c/48c SONET/SDH
application, RPR on 10GbE application,
STS-192c/48c PoS only application
High-level Features
Supports RPR on SONET/SDH, RPR
on 10 GbE, and POS only applications
Maps RPR frames into PoS STS-
192c/48c or STM-64c/16c
Maps RPR frames into 10GbE
10GbE MAC processing, compliant
with IEEE P802.3ae
Integrated on-chip memory
On-chip XAUI mate Serdes
Provides built-in diagnostics
- BERT, loopbacks
SONET/SDH Framer Features
SONET/SDH STS-192c/48c with full
duplex mapping of packets into
SONET/SDH payloads
Pointer and payload processing
Full-duplex TOH add/drop
Performs frame-synchronous scram-
bling and de-scrambling of SONET
Processes section, line and path
overhead bytes
Hardware assistance for APS via K1
and K2 bytes
Semiconductor Solutions for High Speed
Communications and Fiber Optic Applications
The Frea™ is a single-chip OC-192c/48c device that sup-
ports Resilient Packet Ring (RPR) protocol on both
RPR, a layer two Media Access Control (MAC) technology,
significantly increases the bandwidth efficiency of service
provider networks by utilizing twice the capacity of tradi-
tional SONET/SDH rings. RPR delivers dynamic bandwidth
management while preserving the same kind of protection
and resiliency found in SONET/SDH networks.
The Frea chip integrates RPR MAC, PoS (Packet-Over-
SONET) framer and XAUI SerDes (Serializer/Deserializer)
necessary to deploy RPR rings in Metropolitan Area Net-
works (MANs) and Wide Area Networks (WANs). It also
eliminates external memory by including 1 MB of memory
on-chip for RPR operation. The Frea chip supports both
IEEE 802.17 RPR standard Draft 2.1, and RFC 2892 SRP
protocol. It also operates in a PoS framer-only mode,
which allows carriers unparalleled flexibility to build legacy
PoS networks that can later be configured to RPR through
a simple software upgrade.
Detects SEF, LOS, LOF, LOP, and
Monitors line AIS-L, RDI-L, and REI-L
Handles J0 and J1 processing
Calculates, monitors, and counts B1,
B2, and B3 errors
Supports SF/SD BER algorithm
Supports REI-P error counting and
RDI-P monitoring
Supports path unequipped and pay-
load label mismatch
Meets ITU G.707, GR-253, T1.105
PoS Features
PoS on STS-192c/48c
Option of CRC-16 or CRC-32
IETF RFC 2615, RFC 1662
RPR Mac Features
Map RPR frames into SONET/SDH
STS-192c/48c and 10GbE
Supports 802.17 RPR (Draft 2.1) and
RFC-2892 SRP protocols
16 bit HEC with 16-octet RPR header
Supports all traffic classes -
A0/A1/B(EIR and CIR)/C
Supports all fairness-control mecha-
nisms - single and multi-choke fairness
Supports all protection schemes -
steering and wrapping
On-chip low and high priority transit
PM counters
On-chip CAM for address lookup
Edge and core routers
Multi-Service and LAN switches
High-speed servers
PoS and RPR test equipment

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