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HYB39S256400DCL-7 Datasheet(PDF) 8 Page - Infineon Technologies AG

Part # HYB39S256400DCL-7
Description  256-MBit Synchronous DRAM
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

HYB39S256400DCL-7 Datasheet(HTML) 8 Page - Infineon Technologies AG

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HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Pin Configuration
Data Sheet
8
Rev. 1.02, 2004-02
10072003-13LE-FGQQ
2
Pin Configuration
2.1
Signal Pin Description
Table 3
Signal Pin Description
Pin
Type
Signal Polarity Function
CLK
Input
Pulse
Positive
Edge
Clock Input
The system clock input. All of the SDRAM inputs are sampled on the rising
edge of the clock.
CKE
Input
Level
Active
High
Clock Enable
Activates the CLK signal when high and deactivates the CLK signal when
low, thereby initiating either the Power Down mode, Suspend mode, or the
Self Refresh mode.
CS
Input
Pulse
Active
Low
Chip Select
CS enables the command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new
commands are ignored but previous operations continue.
RAS
CAS
WE
Input
Pulse
Active
Low
Command Signals
When sampled at the positive rising edge of the clock, CAS, RAS, and WE
define the command to be executed by the SDRAM.
A0 - A12
Input
Level
Address Inputs
During a Bank Activate command cycle, A0-A12 define the row address
(RA0-RA12) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An define the column address
(CA0-CAn) when sampled at the rising clock edge. CAn depends upon the
SDRAM organization:
64M x4
SDRAM CAn = CA9, CA11 (Page Length = 2048 bits)
32M x8
SDRAM CAn = CA9 (Page Length = 1024 bits)
16M x16 SDRAM CAn = CA8 (Page Length = 512 bits)
In addition to the column address, A10 (= AP) is used to invoke the
autoprecharge operation at the end of the burst read or write cycle. If A10
is high, autoprecharge is selected and BA0, BA1 defines the bank to be
precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in conjunction
with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all
four banks will be precharged regardless of the state of BA0 and BA1. If
A10 is low, then BA0 and BA1 are used to define which bank to precharge.
BA0, BA1 Input
Level
Bank Select
Bank Select Inputs. Bank address inputs selects which of the four banks a
command applies to.
DQx
Input
Output
Level
Data Input/Output
Data Input/Output pins operate in the same manner as on EDO or FPM
DRAMs.
DQM
LDQM
UDQM
Input
Pulse
Active
High
Data Mask
The Data Input/Output mask places the DQ buffers in a high impedance
state when sampled high. In Read mode, DQM has a latency of two clock
cycles and controls the output buffers like an output enable. In Write mode,
DQM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if DQM is high.
One DQM input is present in x4 and x8 SDRAMs, LDQM and UDQM
controls the lower and upper bytes in x16 SDRAMs.


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