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HYS64V16300GU Datasheet(PDF) 8 Page - Infineon Technologies AG

Part No. HYS64V16300GU
Description  3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules
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Maker  INFINEON [Infineon Technologies AG]
Homepage  http://www.infineon.com
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HYS64V16300GU Datasheet(HTML) 8 Page - Infineon Technologies AG

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HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Technologies
8
9.01
Operating Currents per SDRAM Component
T
A = 0 to 70
oC, V
DD = 3.3 V ±0.3 V
Parameter
Test
Condition
Symbol
-7 /7.5
-8
Unit Note
max.
Operating Current
t
RC = tRCMIN., tCK = tCKMIN.
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner
to maximize gapless data access
I
CC1
160
150
mA
1)
Precharge Standby Current
in Power Down Mode
CS =
V
IH (min.), CKE ≤ VIL(MAX)
t
CK =min.
I
CC2P
1.5
1.5
mA
1)
Precharge Stand-by Current
in Non-Power Down Mode
CS =
V
IH (MIN.), CKE ≥ VIH(MIN)
t
CK =min.
I
CC2N
40
35
mA
1)
No Operating Current
t
CK = min., CS = VIH(MIN),
active state (max. 4 banks)
CKE
V
IH(MIN.)
I
CC3N
50
45
mA
1)
CKE
V
IL(MAX.)
I
CC3P
10
10
mA
1)
Burst Operating Current
t
CK =min.,
Read command cycling
I
CC4
100
90
mA
1), 2)
Auto-Refresh Current
t
CK =min.,
Auto-Refresh command cycling
I
CC5
230
210
mA
1)
Self-Refresh Current
Self-Refresh Mode, CKE = 0.2 V
I
CC6
1.5
1.5
mA
1)
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 and 7.5 modules
and at 100 Mhz for -8 modules. Input signals are changed once during t
CK, except for ICC6 and for standby
currents when t
CK = infinity. All values are shown per memory component.
2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3
and BL = 4 assumed and the data-out current is excluded


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