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HYS64V16200GDL Datasheet(PDF) 12 Page - Infineon Technologies AG

Part # HYS64V16200GDL
Description  144 pin SO-DIMM SDRAM Modules
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

HYS64V16200GDL Datasheet(HTML) 12 Page - Infineon Technologies AG

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144 pin SO-DIMM SDRAM Modules
HYS64V16200GDL/HYS64V32220GDL
INFINEON Technologies
12
9.01
SPD-Table HYS64V32220GDL:
Byte#
Description
SPD Entry Value
Hex
32Mx64
-7
32Mx64
-7.5
32Mx64
-8
0
Number of SPD bytes
128
80
1
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses
13
0D
4
Number of Column Addresses
9
09
5
Number of DIMM Banks
2
02
6
Module Data Width
64
40
7
Module Data Width (cont’d)
0
00
8
Module Interface Levels
LVTTL
01
9
SDRAM Cycle Time at CL=3
7.5 / 10.0 ns
75
75
A0
10
SDRAM Access time from Clock at CL=3
5.4 / 6.0 ns
54
54
60
11
Dimm Config (Error Det/Corr.)
none
00
12
Refresh Rate/Type
Self-Refresh, 7.8
µs82
13
SDRAM width, Primary
x16
10
14
Error Checking SDRAM data width
n/a
00
15
Minimum clock delay for back-to-back random
column address
tccd = 1 CLK
01
16
Burst Length supported
1, 2, 4 & 8
0F
17
Number of SDRAM banks
2
04
18
Supported CAS Latencies
2, & 3
06
19
CS Latencies
CS latency = 0
01
20
WE Latencies
Write latency = 0
01
21
SDRAM DIMM module attributes
unbuffered
00
22
SDRAM Device Attributes :General
Vcc tol +/- 10%
0E
23
SDRAM Cycle Time at CL = 2
7.5 / 10 ns
75
A0
24
SDRAM Access Time from Clock at CL=2
5.4 / 6.0 ns
54
60
25
SDRAM Cycle Time at CL = 1
not supported
00
FF
26
SDRAM Access Time from Clock at CL=1
not supported
00
FF
27
Minimum Row Precharge Time
20 ns
0F
14
28
Minimum Row Active to Row Active delay
15 / 16 ns
0E
0F
10
29
Minimum RAS to CAS delay
20 ns
0F
14
30
Minimum Ras pulse width
42 / 45 / 60 ns
2A
2D
32
31
Module Bank Density (per bank)
128MB
20
32
SDRAM input setup time
1.5 / 2 ns
15
15
20
33
SDRAM input hold time
0.8 / 1 ns
08
08
10
34
SDRAM data input setup time
1.5 / 2 ns
15
15
20
35
SDRAM data input hold time
0.8 / 1 ns
08
08
10
36-61
Superset information
00
FF
62
SPD Revision
Revision 1.2
12
63
Checksum for bytes 0 - 62
F5
1E
81
64-125 Manufactures’s information
126
Frequency Specification
64
127
Details
C7
128+
Unused storage locations
FF


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