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HYS64D128320GU-6-A Datasheet(PDF) 13 Page - Infineon Technologies AG |
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HYS64D128320GU-6-A Datasheet(HTML) 13 Page - Infineon Technologies AG |
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13 / 18 page  HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules INFINEON Technologies 13 2002-09-10 (rev.0.81) Electrical Characteristics & AC Timing for DDR-I components (for reference only) (0 °C ≤ T A ≤ 70 °C; VDDQ =2.5V ± 0.2V; VDD =2.5V ± 0.2V) Symbol Parameter DDR333 -6 DDR266A -7 DDR200 -8 Unit Notes Min Max Min Max Min Max t AC DQ output access time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4 t DQSCK DQS output access time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4 t CH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 t CK 1-4 t CL CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 t CK 1-4 t HP Clock Half Period min (t CL, tCH) min (t CL, tCH) min (t CL, tCH) ns 1-4 t CK Clock cycle time CL = 2.5 612 7 12812 ns 1-4 t CK CL = 2.0 7.5 12 7.5 12 10 12 ns 1-4 t DH DQ and DM input hold time 0.45 – 0.5 0.6 ns 1-4 t DS DQ and DM input setup time 0.45 – 0.5 0.6 ns 1-4 t IPW Control and Addr. input pulse width (each input) 2.2 2.2 2.5 ns 1, 10 t DIPW DQ and DM input pulse width (each input) 1.75 1.75 2 ns 1-4, 11 t HZ Data-out high-impedence time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4, 5 t LZ Data-out low-impedence time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4, 5 t DQSS Write command to 1st DQS latching transition 0.75 1.25 0.75 1.25 0.75 1.25 t CK 1-4 t DQSQ DQS-DQ skew (for DQS & associated DQ signals) + 0.4 + 0.5 + 0.6 ns 1-4 t QHS Data hold skew factor + 0.55 – + 0.75 + 1.0 ns 1-4 t QH Data Output hold time from DQS t HP-tQHS t HP-tQHS t HP-tQHS ns 1-4 t DQSL,H DQS input low (high) pulse width (write cycle) 0.35 0.35 0.35 t CK 1-4 t DSS DQS falling edge to CK setup time (write cycle) 0.2 0.2 0.2 t CK 1-4 t DSH DQS falling edge hold time from CK (write cycle) 0.2 0.2 0.2 t CK 1-4 t MRD Mode register set command cycle time 12 14 16 ns 1-4 t WPRES Write preamble setup time 0 0 0 ns 1-4, 7 t WPST Write postamble 0.40 0.60 0.40 0.60 0.40 0.60 t CK 1-4, 6 t WPRE Write preamble 0.25 0.25 0.25 t CK 1-4 t IS Address and control input setup time fast slew rate 0.75 0.9 1.1 ns 2-4, 10,11 slow slew rate 1.0 1.1 ns t IH Address and control input hold time fast slew rate 0.75 0.9 1.1 ns slow slew rate 1.0 1.1 ns t RPRE Read preamble 0.9 0.9 1.1 0.9 1.1 t CK 1-4 t RPST Read postamble 0.40 0.40 0.60 0.40 0.60 t CK 1-4 t RAS Active to Precharge command 42 45 120,000 50 120,000 ns 1-4 t RC Active to Active/Auto-refresh command period 60 65 70 ns 1-4 |
Similar Part No. - HYS64D128320GU-6-A |
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Similar Description - HYS64D128320GU-6-A |
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