HYS64D16301GU datasheet(14/51 Pages) INFINEON

Part #	HYS64D16301GU

Description	184-Pin Unbuffered Dual-In-Line Memory Modules

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Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B

Unbuffered DDR SDRAM Modules

Pin Configuration

Data Sheet

14

V1.1, 2003-07

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DM

I/O 0

I/O 1

I/O 2

I/O 3

D0

DM0/DQS9

I/O 4

I/O 5

I/O 6

I/O 7

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

DM

I/O 0

I/O 1

I/O 2

I/O 3

D1

I/O 4

I/O 5

I/O 6

DM1/DQS10

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

DM

I/O 0

I/O 1

I/O 2

I/O 3

D2

I/O 4

I/O 5

I/O 6

I/O 7

DM2/DQS11

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

DM

I/O 0

I/O 1

I/O 2

I/O 3

D3

I/O 4

I/O 5

I/O 6

I/O 7

DM3/DQS12

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

DM

I/O 0

I/O 1

I/O 2

I/O 3

D4

DM4/DQS13

I/O 4

I/O 5

I/O 6

I/O 7

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

DM

I/O 0

I/O 1

I/O 2

I/O 3

D5

I/O 4

I/O 5

I/O 6

I/O 7

DM5/DQS14

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

DM

I/O 0

I/O 1

I/O 2

I/O 3

D6

I/O 4

I/O 5

I/O 6

I/O 7

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

DM

I/O 0

I/O 1

I/O 2

I/O 3

D7

I/O 4

I/O 5

I/O 6

I/O 7

DM7/DQS16

A0 - A13

A0-A13: SDRAMs D0 - D8

A0

Serial PD

A1

A2

SA0

SA1

SA2

SDA

RAS

RAS: SDRAMs D0 - D8

CAS

CAS: SDRAMs D0 - D8

CKE0

CKE: SDRAMs D0 - D8

WE

WE: SDRAMs D0 - D8

S0

S

BA0 - BA1

BA0-BA1: SDRAMs D0 - D8

DQS0

DQS

DQS4

DQS1

DQS5

DQS

DQS2

DQS

DQS3

DQS

DM6/DQS15

DQS6

DQS7

DQ15

I/O 7

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

DM

I/O 0

I/O 1

I/O 2

I/O 3

D8

I/O 4

I/O 5

I/O 6

I/O 7

S

DQS8

DM8/DQS17

DQS

* Clock Wiring

*CK0/CK0

Clock

Input

SDRAMs

*CK1/CK1

3 SDRAMs

* Wire per Clock Loading

Table/Wiring Diagrams

*CK2/CK2

VSS

D0 - D8

VDD/VDDQ

D0 - D8

VREF

VDDID

Strap: see Note 4

Notes:

1. DQ-to-I/O wiring is shown as recommended

but may be changed.

2. DQ/DQS/DM/CKE/S relationships must be

maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

STRAP IN (VSS): VDD ≠ VDDQ.

5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohm

+5%

SCL

WP

SPD

VDDSPD

Figure 4

Block Diagram - One Rank 32M

× 72 DDR-I SDRAM DIMM HYS72D32x00GU using × 8

organized SDRAMs

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