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HYE18P32160ACL15 Datasheet(PDF) 11 Page - Infineon Technologies AG |
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HYE18P32160ACL15 Datasheet(HTML) 11 Page - Infineon Technologies AG |
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11 / 53 page  Data Sheet 11 V2.0, 2003-12-16 HYE18P32160AC(-/L)9.6/12.5/15 32M Synchronous Burst CellularRAM Overview 1.4 HYE18P32160AC(-/L)9.6/12.5/15 Ball Definition and Description Table 2 Ball Description - HYE18P32160AC(-/L)9.6/12.5/15 Ball Type Detailed Function CLK Input Clock Signal In synchronous burst mode, address and command inputs and data are referenced to CLK. In asynchronous SRAM-type mode the clock signal is ignored. During write accesses in NOR-Flash operation mode the CLK signal must be clamped to low. CRE Input Control Register Enable CRE set to high enables the access to the control register map. By applying the SET CONTROL REGISTER (SCR) command (see Table 3) the address bus is loaded into the selected control register. ADV Input Address Valid ADV signals in NOR-Flash and full synchronous mode that a valid address is present on the address bus. In NOR-Flash read mode and full synchronous mode the address is latched on the programmed clock edge while ADV is held low. In NOR-Flash write mode ADV can be used to latch the address, but can be held low as well. In asynchronous SRAM-type mode ADV needs to be active, it may be tied to active. CS Input Chip Select CS enables the command decoder when low and disables it when high. When the command decoder is disabled new commands are ignored, addresses are don’t care and outputs are forced to high-Z. Internal operations, however, continue. For the details please refer to the command tables in Chapter 1.6. OE Input Output Enable OE controls DQ output driver. OE low drives DQ, OE high sets DQ to high-Z. WE Input Write Enable WE set to low while CS is low initiates a write command. UB, LB Input Upper/Lower Byte Enable UB enables the upper byte DQ15-8 (resp. LB DQ7 … 0) during read/write operations. UB (LB) deassertion prevents the upper (lower) byte from being driven during read or being written. WAIT Output 3-state Wait State Signal In synchronous mode, WAIT signal indicates the host system when the output data is valid during read and when the input data should be asserted during write operation. In asynchronous mode, the signal has to be ignored. A <20:0> Input Address Inputs During a Control Register Set operation by CRE access, the address inputs define the register settings. DQ <15:0> I/O Data Input/Output The DQ signals 0 to 15 form the 16-bit data bus. 1 × V DD 1 × V SS Power Supply Power Supply, Core Power and Ground for the internal logic. 1 × V DDQ 1 × V SSQ Power Supply Power Supply, I/O Buffer Isolated Power and Ground for the output buffers to provide improved noise immunity. 4 × NC – No Connect Please do not connect. Reserved for future use, i.e. E3: A21, J4: A22, see ballout in Figure 2 on Page 10. |
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