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HYE25L256160AC-8 Datasheet(PDF) 10 Page - Infineon Technologies AG |
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HYE25L256160AC-8 Datasheet(HTML) 10 Page - Infineon Technologies AG |
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10 / 55 page  HYE25L256160AC 256-Mbit Mobile-RAM Functional Description Data Sheet 10 V1.1, 2003-04-16 3 Functional Description The 256-Mbit Mobile-RAM is a new generation of low power, four bank synchronous DRAM organized as 4banks × 4Mbit × 16 with additional features for mobile applications. The synchronous Mobile-RAM achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The device adds new features to the industry standards set for synchronous DRAM products. Parts of the memory array can be selected for Self-Refresh and the refresh period during Self-Refresh is programmable in 4 steps which drastically reduces the self refresh current, depending on the case temperature of the components in the system application. In addition a “Deep Power Down Mode” is available. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Prior to normal operation, the 256-Mbit Mobile-RAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. 3.1 Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the 256-Mbit Mobile-RAM must be powered up and initialized in a predefined manner. V DD must be applied before or at the same time as V DDQ to the specified voltage when the input signals are held in the “NOP” or “DESELECT” state. The power on voltage must not exceed V DD + 0.3 V on any of the input pins or VDDQ supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 ms is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.Mode Register Definition 3.2 Mode Register The Mode Register designates the operation mode at the read or write cycle. This register is divided into four fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), and a CAS Latency Field to set the access time at clock cycle, an The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table. BA0 and BA1 have to be set to “0” to enter the Mode Register. |
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