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XIO2001ZAJ Datasheet(PDF) 11 Page - Texas Instruments |
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XIO2001ZAJ Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 141 page  11 XIO2001 www.ti.com SCPS212I – MAY 2009 – REVISED JANUARY 2016 Product Folder Links: XIO2001 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Pin Functions (continued) SIGNAL ZGU BALL NO. ZAJ BALL NO. PNP PIN NO. I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS DESCRIPTION PCI SYSTEM AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 N05 N04 L05 M05 N03 M04 N02 M03 L04 M02 L03 M01 L02 L01 K02 K01 E01 E02 E03 D01 D02 C01 C02 D03 C03 B02 C04 A02 B03 B04 A03 C05 N05 L05 M05 N04 N03 L04 M04 N02 L03 M02 N01 L02 K02 M01 K03 L01 F02 E03 E01 E02 D01 C01 D02 B01 A01 B03 C03 A02 A03 C04 C05 B04 44 43 42 41 40 39 38 37 35 34 32 31 30 29 28 26 12 11 10 9 8 6 5 4 1 128 127 125 124 123 122 121 I/O PCI Bus PCIR – PCI address data lines C/BE[3] C/BE[2] C/BE[1] C/BE[0] N01 J03 F02 B01 M03 K01 F03 C02 36 25 14 3 I/O PCI Bus PCIR – PCI command byte enables CLK F03 F01 13 I PCI Bus PCIR – PCI clock input. This is the clock input to the PCI bus core. CLKOUT0 CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKOUT6 B05 B06 A07 B07 A09 A10 B11 B05 B06 B07 A07 A08 A10 C10 120 117 114 112 107 104 99 O PCI Bus PCIR – PCI clock outputs. These clock outputs are used to clock the PCI bus. If the bridge PCI bus clock outputs are used, then CLKOUT6 must be connected to the CLK input. DEVSEL H02 H02 20 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI device select FRAME J02 J01 24 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI frame GNT5 GNT4 GNT3 GNT2 GNT1 GNT0 B10 A11 B09 B08 C06 A05 B11 B10 B09 B08 A06 A05 101 103 106 109 115 118 O PCI Bus PCIR – PCI grant outputs. These signals are used for arbitration when the PCI bus is the secondary bus and an external arbiter is not used. GNT0 is used as the REQ for the bridge when an external arbiter is used. INTA INTB INTC INTD M06 N06 M07 L07 N06 L06 M07 N07 47 48 49 50 I PCI Bus PCIR Pullup resistor per PCI spec PCI interrupts A–D. These signals are interrupt inputs to the bridge on the secondary PCI bus. IRDY J01 H03 23 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI initiator ready LOCK M08 N08 54 I/O PCI Bus PCIR Pullup resistor per PCI spec This terminal functions as PCI LOCK Note: In lock mode, an external pullup resistor is required to prevent the LOCK signal from floating. |
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