HYB 39S512[40/80/16]0AT(L)

512-Mbit Synchronous DRAM

Overview

Data Sheet

8

Rev. 1.3, 2004-03

10082003-L1GD-PVI5

1

Overview

1.1

Features

•

Fully Synchronous to Positive Clock Edge

•0 to 70

°C operating temperature

•

Four Banks controlled by BA0 & BA1

•

Programmable CAS Latency: 2 & 3

•

Programmable Wrap Sequence: Sequential or Interleave

•

Programmable Burst Length: 1, 2, 4, 8 and full page

•

Multiple Burst Read with Single Write Operation

•

Automatic and Controlled Precharge Command

•

Data Mask for Read / Write control (

×4, ×8)

•

Data Mask for byte control (

×16)

•

Auto Refresh (CBR) and Self Refresh

•

Power Down and Clock Suspend Mode

•

8192 refresh cycles / 64 ms (7,8

µs)

•

Random Column Address every CLK ( 1-N Rule)

•

Single 3.3 V

± 0.3 V Power Supply

•

LVTTL Interface versions

•

Plastic Packages:

P-TSOPII-54 400mil width (x4, x8, x16)

1.2

Description

The HYB 39S512[40/80/16]0AT(L) are four bank Synchronous DRAM’s organized as 4 banks

× 32MBit ×4, 4

banks

× 16MBit ×8 and 4 banks × 8Mbit ×16 respectively. These synchronous devices achieve high speed data

transfer rates

for CAS-latencies by employing a chip architecture that prefetches multiple bits and then

synchronizes the output data to a system clock. The chip is fabricated with INFINEON’s advanced 0.14

µm

512MBit DRAM process technology.

The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically

and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge

of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate

than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length,

CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3 V

± 0.3 V

power supply. All 512Mbit components are housed in P-TSOPII-54 packages.

Table 1

Performance

Part Number Speed Code

–7

–7.5

–8Unit

Speed Grade

PC133 2–2–2

PC133 3–3–3

PC100 2–2–2

–

max. Clock Frequency

@CL3

f

CK

143

133

125

MHz

t

CK3

77.5

8ns

t

AC3

5.4

5.4

6

ns

@CL2

t

CK2

7.5

10

10

ns

t

AC2

5.4

6

6

ns