HYB39L256160AT-8 datasheet(1/48 Pages) INFINEON

Part #	HYB39L256160AT-8

Description	256 MBit Synchronous Low-Power DRAM

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Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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HYB39L256160AC/T

256 MBit 3.3V Mobile-RAM

INFINEON Technologies AG

1

2002-12-20

Description

The HYB 39L256160AC Mobile-RAM is a new generation of low power, four bank Synchronous

DRAM’s organized as 4 banks x 4 Mbit x 16. These synchronous Mobile-RAMs achieve high speed

data transfer rates by employing a chip architecture that prefetches multiple bits and then

synchronizes the output data to a system clock.

All of the control, address, data input and output circuits are synchronized with the positive edge of

an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur

at higher rate. A sequential and gapless data rate is possible depending on burst length,

CAS

latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. The device operates with a single

3.3 V

±0.3V power supply.

Compared to conventional SDRAM the self-refresh current is further reduced. The Mobile-RAM

devices are available in FBGA “chip-size” or TSOPII packages.

Features

• 16 Mbit x16 organisation

• VDD = VDDQ = 3.3 V

• Fully Synchronous to Positive Clock Edge

• Four Banks controlled by BA0 & BA1

• Programmable

CAS Latency: 2, 3

• Programmable Wrap Sequence: Sequential

or Interleave

• Automatic and Controlled Precharge

Command

• Programmable Burst Length: 1, 2, 4, 8 and

full page

• Data Mask for byte control

• Auto Refresh (CBR)

• 8192 Refresh Cycles / 64ms

• Very low Self Refresh current

• Power Down and Clock Suspend Mode

• Random Column Address every CLK

(1-N Rule)

• P-TFBGA-54, with 9 x 6 ball array with

3 depopulated rows, 12 x 8 mm

2

• P-TSOPII-54 alternate package

• Operating Temperature Range

Commerical (00 to 700C)

-7.5

-8

Units

f

CK,MAX

133

125

MHz

t

CK3,MIN

7.5

8

ns

t

AC3,MAX

5.4

6

ns

t

CK2,MIN

9.5

ns

t

AC2,MAX

66ns

256 MBit Synchronous Low-Power DRAM

Data Sheet Revision Dec. 2002

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