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74F161ASJ Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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74F161ASJ Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 10 page Functional Description The ’F161A and ’F163A count in modulo-16 binary se- quence From state 15 (HHHH) they increment to state 0 (LLLL) The clock inputs of all flip-flops are driven in parallel through a clock buffer Thus all changes of the Q outputs (except due to Master Reset of the ’F161A) occur as a re- sult of and synchronous with the LOW-to-HIGH transition of the CP input signal The circuits have four fundamental modes of operation in order of precedence asynchronous reset (’F161A) synchronous reset (’F163A) parallel load count-up and hold Five control inputsMaster Reset (MR ’F161A) Synchronous Reset (SR ’F163A) Parallel Enable (PE) Count Enable Parallel (CEP) and Count Enable Trickle (CET)determine the mode of operation as shown in the Mode Select Table A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP A LOW signal on PE overrides counting and allows informa- tion on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP With PE and MR (’F161A) or SR (’F163A) HIGH CEP and CET permit count- ing when both are HIGH Conversely a LOW signal on ei- ther CEP or CET inhibits counting The ’F161A and ’F163A use D-type edge triggered flip-flops and changing the SR PE CEP and CET inputs when the CP is in either state does not cause errors provided that the recommended setup and hold times with respect to the ris- ing edge of CP are observed The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in state 15 To implement synchronous multi-stage counters the TC outputs can be used with the CEP and CET inputs in two different ways Please refer to the ’F568 data sheet The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops counters or registers Logic Equations Count Enable e CEP CET PE TC e Q0 Q1 Q2 Q3 CET Mode Select Table SR PE CET CEP Action on the Rising Clock Edge ( L) L X X X Reset (Clear) H L X X Load (Pn xQn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold) For ’F163A only H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial State Diagram TLF9486 – 5 3 |
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