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HYE25L128160AC-75 Datasheet(PDF) 10 Page - Infineon Technologies AG |
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HYE25L128160AC-75 Datasheet(HTML) 10 Page - Infineon Technologies AG |
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10 / 50 page  HYB/E 25L128160AC 128-MBit Mobile-RAM INFINEON Technologies 10 2003-02 @rqrqÃHqrÃSrtvr
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hv When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, W RCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 133 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organisation and column addressing. Full page burst operation does not self terminate once the burst length has been reached. In other words, unlike burst length of 2, 4 and 8, full page burst continues until it is terminated using another command. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax) Mode Register (Mx) M4 M3 0 0 1 0 0 1 1 1 M1 M0 M2 1 0 0 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 1 1 0 0 0 1*) 0*) *)BA1 and BA0 must be 1, 0 to select the Extended Mode Register (Vs. the Mode Register) TCR PASR Temperature-Compensated Self-Refresh: max. case temp. 45 C 0 70 C 0 85 C 0 15 C 0 Partial-Array Self Refresh: banks to be self-refreshed all banks 1/2 array (BA1=0) 1/4 array (BA1=0, BA0=0) Reserved Reserved 1/8 array (BA1=BA0=0, RA11=0) Reserved all have to be set to "0" 1/16 array (BA1=BA0=0, RA11=RA10=0) |
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