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HYB25D128160CT-6 Datasheet(PDF) 10 Page - Infineon Technologies AG |
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HYB25D128160CT-6 Datasheet(HTML) 10 Page - Infineon Technologies AG |
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10 / 85 page  HYB25D128[400/800/160]C[C/E/T](L) 128 Mbit Double Data Rate SDRAM Pin Configuration Data Sheet 10 Rev. 1.0, 2004-04 2 Pin Configuration The pin configuration of a DDR SDRAM is listed by function in Table 2 (60 pins). The abbreviations used in the Pin#/Buffer# column are explained in Table 3 and Table 4 respectively. The pin numbering for FBGA is depicted in Figure 1 and that of the TSOP package in Figure 2 Table 2 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type Buffer Type Function Clock Signals G2, 45 CK1 I SSTL Clock Signal Note: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). G3, 46 CK1 I SSTL Complementary Clock Signal H3, 44 CKE I SSTL Clock Enable Note: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power- down. Input buffers, excluding CKE, are disabled during self refresh. Control Signals H7, 23 RAS I SSTL Row Address Strobe G8, 22 CAS I SSTL Column Address Strobe G7, 21 WE I SSTL Write Enable H8, 24 CS I SSTL Chip Select Note: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. The standard pinout includes one CS pin. Address Signals J8, 26 BA0 I SSTL Bank Address Bus 2:0 Note: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. J7, 27 BA1 I SSTL |
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