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SAF-C164CI Datasheet(PDF) 10 Page - Infineon Technologies AG |
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SAF-C164CI Datasheet(HTML) 10 Page - Infineon Technologies AG |
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10 / 79 page  C164CI/SI C164CL/SL Data Sheet 6 V2.0, 2001-05 P4 P4.0 P4.1 P4.2 P4.3 P4.5 P4.6 17 18 19 22 23 24 IO O O O O O O O O O I O O Port 4 is a 6-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 4 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 4 is selectable (TTL or special). Port 4 can be used to output the segment address lines, the optional chip select lines, and for serial interface lines:1) A16 Least Significant Segment Address Line, CS3 Chip Select 3 Output A17 Segment Address Line, CS2 Chip Select 2 Output A18 Segment Address Line, CS1 Chip Select 1 Output A19 Segment Address Line, CS0 Chip Select 0 Output A20 Segment Address Line, CAN1_RxD CAN 1 Receive Data Input A21 Most Significant Segment Address Line, CAN1_TxD CAN 1 Transmit Data Output RD 25 O External Memory Read Strobe. RD is activated for every external instruction or data read access. WR/ WRL 26 O External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. ALE 27 O Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. Table 2 Pin Definitions and Functions (cont’d) Symbol Pin No. Input Outp. Function |
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