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HYE18L256160BF-75 Datasheet(PDF) 9 Page - Infineon Technologies AG |
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HYE18L256160BF-75 Datasheet(HTML) 9 Page - Infineon Technologies AG |
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9 / 49 page  HY[B/E]18L256160B[C/F]-7.5 256-Mbit Mobile-RAM Overview Data Sheet 9 V1.4, 2004-04-30 1.3 Description The HY[B/E]18L256160B[C/F] is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The HY[B/E]18L256160B[C/F] achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are burst-oriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4, 8 or full page) in a programmed sequence. The device operation is fully synchronous: all inputs are registered at the positive edge of CLK. The HY[B/E]18L256160B[C/F] is especially designed for mobile applications. It operates from a 1.8V power supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR). A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power- Down (DPD) mode. The HY[B/E]18L256160B[C/F] is housed in a 54-ball P-VFBGA package. It is available in Commercial (0 °C to 70 °C) and Extended (-25 °C to +85 °C) temperature range. Figure 2 Functional Block Diagram CKE CLK CS RAS CAS WE 13 Mode Registers 13 Column Address Counter / Latch 9 Bank 0 Memory Array (8192 x 512 x 16) Sense Amplifier 8192 IO Gating DQM Mask Logic Column Decoder 9 15 A0-A12 BA0,BA1 16 DQ0- DQ15 Data Output Reg. Data Input Reg. 16 LDQM UDQM Bank 1 Bank 2 Bank 3 2 2 2 2 |
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