1

2

3

4

5

6

7

8

9

S

1

1

1

0

1

A

A

10.x

A

11.x

A

10.x

1

11.x

P

R/W

SCL

SDA

INT

00

10

03

12

Read From Port 0

Data Into Port 0

Read From Port 1

Data Into Port 1

Data 02

Data 01

Data 00

Data 03

Data 12

Data 11

Data 10

Acknowledge

From Slave

Acknowledge

From Master

Acknowledge

From Master

Acknowledge

From Master

No Acknowledge

From Master

1

A1 A0

1

2

3

4

5

6

7

8

9

S

1

1

1

0

1

A

7

6

5

4

3

2

1

0

A

10.x

7

6

5

4

3

2

1

0

A

11.x

7

6

5

4

3

2

1

0

A

10.x

7

6

5

4

3

2

1

0

1

11.x

P

R/W

SCL

SDA

INT

Read From Port 0

Data Into Port 0

Read From Port 1

Data Into Port 1

Acknowledge

From Master

Acknowledge

From Slave

Acknowledge

From Master

Acknowledge

From Master

No Acknowledge

From Master

1

A1 A0

24

TCA9539

SCPS202B – OCTOBER 2009 – REVISED OCTOBER 2015

www.ti.com

Product Folder Links: TCA9539

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Copyright © 2009–2015, Texas Instruments Incorporated

Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number

of data bytes received in one read transmission, but when the final byte is received, the bus master must not

acknowledge the data.

A.

Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest

acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read

Input Port register).

B.

This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address

call and actual data transfer from the P port (see Figure 31 for these details).

Figure 32. Read Input Port Register, Scenario 1

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A.

Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest

acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read

Input Port register).

B.

This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address

call and actual data transfer from the P port (see Figure 31 for these details).

Figure 33. Read Input Port Register, Scenario 2