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SN65HVD1781QDRQ1 Datasheet(PDF) 4 Page - Texas Instruments |
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SN65HVD1781QDRQ1 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 28 page 4 SN65HVD1780-Q1, SN65HVD1781-Q1, SN65HVD1782-Q1 SLLSE49B – SEPTEMBER 2010 – REVISED JANUARY 2016 www.ti.com Product Folder Links: SN65HVD1780-Q1 SN65HVD1781-Q1 SN65HVD1782-Q1 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.2 ESD Ratings—AEC VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) Bus terminals and GND ±16000 V All pins ±4000 Charged-device model (CDM), per AEC Q100-011 ±2000 Machine Model (MM), AEC-Q100-003 ±400 6.3 ESD Ratings—IEC VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per IEC 60749-26 Bus terminals and GND ±16000 V (1) By convention, the least positive (most negative) limit is designated as minimum in this data sheet. 6.4 Recommended Operating Conditions MIN NOM MAX UNIT VCC Supply voltage 3.15 5 5.5 V VI Input voltage at any bus terminal (separately or common mode)(1) –7 12 V VIH High-level input voltage (driver, driver enable, and receiver enable inputs) 2 VCC V VIL Low-level input voltage (driver, driver enable, and receiver enable inputs) 0 0.8 V VID Differential input voltage –12 12 V IO Output current, driver –60 60 mA Output current, receiver –8 8 mA RL Differential load resistance 54 60 Ω CL Differential load capacitance 50 pF 1/tUI Signaling rate SN65HVD1780-Q1 115 Mbps SN65HVD1781-Q1 1 SN65HVD1782-Q1 10 TA Operating free-air temperature (See the Thermal Information table) 5-V supply –40 105 °C 3.3-V supply –40 125 TJ Junction Temperature –40 150 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Thermal Information THERMAL METRIC(1) SN65HVD1780-Q1 SN65HVD1781-Q1 SN65HVD1782-Q1 UNIT D (SOIC) 8 PINS RθJA Junction-to-ambient thermal resistance JEDEC high-K model 138 °C/W JEDIC low-K model 242 °C/W RθJC(top) Junction-to-case (top) thermal resistance 61 °C/W RθJB Junction-to-board thermal resistance 62 °C/W ψJT Junction-to-top characterization parameter 3.8 °C/W ψJB Junction-to-board characterization parameter 38.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W |
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