SN65HVD11-HT

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SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

6.2 ESD Ratings

VALUE

UNIT

A, B, and GND

±16000

Electrostatic

All pins

±4000

V

discharge

±1000

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

Supply voltage

3

3.6

V

Voltage at any bus terminal (separately or common-mode)

12

V

High-level input voltage

D, DE, RE

2

V

Low-level input voltage

D, DE, RE

0

0.8

V

Differential input voltage

Figure 16

–12

12

V

Driver

–60

High-level output current

mA

Receiver

–8

Driver

60

Low-level output current

mA

Receiver

8

Differential load resistance

54

60

Ω

Differential load capacitance

50

pF

Signaling rate

10

Mbps

129

(2)

Operating junction temperature

179

°C

214

(1)

The algebraic convention, in which the least-positive (most-negative) limit is designated as minimum, is used in this data sheet.

(2)

See Thermal Information table for information regarding this specification.

6.4 Thermal Information

SN65HVD11-HT

D (SOIC)

JD (CDIP SB)

HKJ (CFP)

HKQ (CFP)

UNIT

8 PINS

8 PINS

8 PINS

8 PINS

Junction-to-ambient thermal resistance

101.5

73.9

N/A

170

°C/W

53.6

N/A

N/A

6.2

°C/W

Junction-to-board thermal resistance

45.1

39.8

N/A

195

°C/W

Junction-to-top characterization parameter

4.8

6.9

N/A

3.8

°C/W

Junction-to-board characterization parameter

41.8

49.2

N/A

146.8

°C/W

N/A

9.1

6.2

N/A

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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