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DS125RT410SQ Datasheet(PDF) 4 Page - Texas Instruments |
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DS125RT410SQ Datasheet(HTML) 4 Page - Texas Instruments |
4 / 58 page DS125RT410 SNLS459A – APRIL 2013 – REVISED OCTOBER 2015 www.ti.com Pin Functions (continued) PIN I/O, TYPE (1) DESCRIPTION NAME NO. LOOP FILTER CONNECTION PINS LPF_CP_0 47 Loop filter connection I/O, analog LPF_REF_0 48 Place a 22 nF ± 10% capacitor between LPF_CP_0 and LPF_REF_0 LPF_CP_1 38 Loop filter connection I/O, analog LPF_REF_1 37 Place a 22 nF ± 10% capacitor between LPF_CP_1 and LPF_REF_1 LPF_CP_2 23 Loop filter connection I/O, analog LPF_REF_2 24 Place a 22 nF ± 10% capacitor between LPF_CP_2 and LPF_REF_2 LPF_CP_3 14 Loop filter connection I/O, analog LPF_REF_3 13 Place a 22 nF ± 10% capacitor between LPF_CP_3 and LPF_REF_3 REFERENCE CLOCK I/O Input is 2.5 V, 25 MHz ± 100-ppm reference clock from external oscillator REFCLK_IN 19 I, 2.5-V analog No stringent phase noise requirement O, 2.5-V Output is 2.5 V, buffered replica of reference clock input for connecting multiple DS125RT410 REFCLK_OUT 42 analog devices on a board LOCK INDICATOR PINS LOCK0 45 LOCK1 40 O, 2.5-V Output is 2.5 V, the pin is high when CDR lock is attained on the corresponding channel. LOCK2 21 LVCMOS These pins are shared with SMBus address strap input functions read at start-up. LOCK3 16 SMBus MASTER MODE PINS O, 2.5-V Output is 2.5 V, the pin goes low to indicate that the SMBus master EEPROM read has been ALL_DONE 41 LVCMOS completed. I, 2.5-V Input is 2.5 V, a transition from high to low starts the load from the external EEPROM. The READ_EN 44 LVCMOS READ_EN pin must be tied low when in SMBus slave mode. INTERRUPT OUTPUT Used to signal horizontal or vertical eye opening out of tolerance, loss of signal detect, or O, 3.3-V CDR unlock. INT 43 LVCMOS, External 2-k Ω to 5-kΩ pullup resistor is required. Open Drain Pin is 3.3-V LVCMOS tolerant. SERIAL MANAGEMENT BUS (SMBus) INTERFACE Input is 2.5 V, selects SMBus master mode or SMBus slave mode. EN_SMB = High for slave mode EN_SMB 20 I, 2.5-V analog EN_SMB = Float for master mode Tie READ_EN pin low for SMBus slave mode. See Table 4. I/O, 3.3-V Data Input and Open Drain Output SDA 18 LVCMOS, External 2-k Ω to 5-kΩ pullup resistor is required. Open Drain Pin is 3.3-V LVCMOS tolerant. I/O, 3.3-V Clock Input and Open Drain Clock Output SDC 17 LVCMOS, External 2-k Ω to 5-kΩ pullup resistor is required. Open Drain Pin is 3.3-V LVCMOS tolerant. Input is 2.5 V, the ADDR_[3:0] pins set the SMBus address for the retimer. ADDR_0 45 These pins are strap inputs. Their state is read on power-up to set the SMBus address in ADDR_1 40 I, 2.5-V SMBus control mode. ADDR_2 21 LVCMOS High = 1 k Ω to VDD, Low = 1 kΩ to GND ADDR_3 16 These pins are shared with the lock indicator functions. See Table 1. POWER 3, 6, 7, VDD 10, 15, Power VDD = 2.5 V ± 5% 46 22, 27, GND 30, 31, Power Ground reference. 34, 39 Ground reference. The exposed pad at the center of the package must be connected to DAP PAD Power ground plane of the board with at least 4 vias to lower the ground impedance and improve the thermal performance of the package. 4 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: DS125RT410 |
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