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DS125RT410 Datasheet(PDF) 17 Page - Texas Instruments |
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DS125RT410 Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 58 page  DS125RT410 www.ti.com SNLS459A – APRIL 2013 – REVISED OCTOBER 2015 For the entries in Table 3 where the divider ratios are the same for the two groups, the expected PPM count for the two groups does not have to be the same. Therefore, in ref_mode 3, a single set of register settings can be used to specify multiple VCO frequencies either with the same divider ratio or with different divider ratios. 7.4.4.1 Ref_mode 3 Mode (Reference Clock Required) Ref_mode 3 requires an external 25-MHz clock. This mode of operation is set in register 0x36 bits [5:4] = 2'b11 and is the default setting. In ref_mode 3, the external reference clock is used to aid initial phase lock, and to determine when its VCO is properly phase-locked. An external oscillator should be used to generate a 2.5-V, 25-MHz reference signal that is connected to the DS125RT410 on the reference clock input pin (pin 19). The DS125RT410 does not include a crystal oscillator circuit, so a stand-alone external oscillator is required. The reference clock speeds up the initial phase lock acquisition. The DS125RT410 is set to phase lock to a known data rate, or a constrained set of known data rates, and the digital circuitry in the DS125RT410 preconfigures the VCO frequency. This enables the DS125RT410 phase-lock to the incoming signal very quickly. The reference clock is used to calibrate the VCO coarse tuning. However, the reference clock is not synchronous to the data stream, and the quality of the reference clock does not affect the jitter on the output retimed data. The retimed data clock for each channel is synchronous to the VCO internal to that channel of the DS125RT410. The phase noise of the reference clock is not critical. Any commercially-available 25-MHz oscillator can provide an acceptable reference clock. The reference clock can be daisy-chained from one retimer to another so that only one reference oscillator is required in a system. 7.4.4.2 False Lock Detector Setting The register 0x2F, bit 1 is set to 1 by default, which disables the false lock detector. This bit must be set to 0 to enable the false lock detector function. 7.4.4.3 Reference Clock In REFCLK_IN pin 19 is for reference clock input. A 25-MHz oscillator should be connected to pin 19. See Electrical Characteristics for the requirements on the 25-MHz clock. The frequency of the reference clock should always be 25 MHz no matter what data rate or mode of operation is used. 7.4.4.4 Reference Clock Out REFCLK_OUT pin 42 is the reference clock output pin. The DS125RT410 drives a buffered replica of the 25-MHz reference clock input on this output pin. If there are multiple DS125RT410 in the system, the REFCLK_OUT pin can be directly connected to the REFCLK_IN pin of another DS125RT410 in a daisy chain connection. The number of devices cascaded in a REF_CLK daisy chain is affected by the effective capacitance of the board trace connecting the REFCLK_OUT of one device to the REF_IN of the next device. The pulse high duration at the input of the last device must be greater than 4 ns for proper operation. In cases of cascading daisy chain with short trace (around 1.5 inches or 5-pf trace capacitance), it is possible to cascade up to nine devices. In other systems with longer interconnecting trace or more capacitive loading, the max number of daisy chained devices would be smaller. In a system that requires longer daisy chain, TI recommends placing an inverted gate after the sixth device. the pre-distorted duty cycle from the inverter allows for longer daisy chain. a better approach is to break the long daisy chain into two shorter chains, each driven by a buffer version of the clock and with each chain kept to a maximum of 6. As an example, if there are 12 devices in the system, the daisy chain connections can be divided into two groups of 6 devices and PCB trace length for the reference clock output to input connection should be 1.5 inches or less. 7.4.4.5 Driver Output Voltage The differential output voltage of the DS125RT410 can be configured from a nominal setting of 600-mV peak-to- peak differential to a nominal setting of 1.3-V peak-to-peak differential, depending upon the application. The driver output voltage as set is the typical peak-to-peak differential output voltage with no de-emphasis enabled. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: DS125RT410 |
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