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DS90UH948TNKDRQ1 Datasheet(PDF) 5 Page - Texas Instruments |
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DS90UH948TNKDRQ1 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 91 page  5 DS90UH948-Q1 www.ti.com SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016 Product Folder Links: DS90UH948-Q1 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O, TYPE DESCRIPTION NAME NUMBER D6- D6+ 26 25 O, LVDS Channel 6 Differential Output This pair requires an external 100 Ω termination for LVDS D7- D7+ 22 21 O, LVDS Channel 7 Differential Output This pair requires an external 100 Ω termination for LVDS FPD-LINK III INTERFACE - Layout note: for unused FPD-LinkIII inputs, float those pins (do not connect to an external pullup or pulldown) RIN0- 54 I/O, CML FPD-Link III Inverting Input/Output The output must be AC-coupled with a 33 nF capacitor. RIN0+ 53 I/O, CML FPD-Link III True Input/Output The output must be AC-coupled with a 33 nF capacitor. RIN1- 59 I/O, CML FPD-Link III Inverting Input/Output The output must be AC-coupled with a 33 nF capacitor. RIN1+ 58 I/O, CML FPD-Link III True Input/Output The output must be AC-coupled with a 33 nF capacitor. CMF 55 I/O, CML Common Mode Filter. Connect 0.1 µF capacitor to GND I2C PINS I2C_SDA 46 I/O, Open- Drain I2C Data Input / Output interface Open drain. Must have an external pull-up resistor to VDDIO DO NOT FLOAT. Recommended pull-up: 4.7 k Ω. I2C_SCL 45 I/O, Open- Drain I2C Clock Input / Output Interface Open drain. Must have an external pull-up resistor to VDDIO DO NOT FLOAT. Recommended pull-up: 4.7 k Ω. IDx 47 I, Analog Configuration Pin Analog input. I2C Serial Control Bus Device ID Address. Table 10 SPI PINS (Pin function programmed through register) - Layout note: for unused SPI pins, tie to an external pulldown MOSI (D_GPIO0) 19 Multi-function pin I/O, LVCMOS w/ weak internal PD Master Out, Slave In. (Pin is shared with D_GPIO0) MISO (D_GPIO1) 18 Multi-function pin I/O, LVCMOS w/ weak internal PD Master In, Slave Out. (Pin is shared with D_GPIO1) SPLK (D_GPIO2) 17 Multi-function pin I/O, LVCMOS w/ weak internal PD Serial clock. (Pin is shared with D_GPIO2) SS (D_GPIO3) 16 Multi-function pin I/O, LVCMOS w/ weak internal PD Slave select. (Pin is shared with D_GPIO3) CONTROL PINS MODE_SEL0 61 I, Analog Configuration Pin Analog input. Mode Select 0. Connect to external pull-up to VDD33 and pull-down to GND to create a voltage divider. See Configuration Select (MODE_SEL0) Table 8 MODE_SEL1 50 I, Analog Configuration Pin Analog input. Mode Select 1. Connect to external pull-up to VDD33 and pull-down to GND to create a voltage divider. See Configuration Select (MODE_SEL1) Table 9 |
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