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DAC8162SDGSR Datasheet(PDF) 4 Page - Texas Instruments |
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DAC8162SDGSR Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 60 page  SYNC SCLK D IN AV DD V /V REFIN REFOUT 1 2 3 4 5 6 7 8 9 10 V A OUT V B OUT GND LDAC CLR Thermal Pad (1) V A OUT V B OUT GND LDAC CLR 1 2 3 4 5 6 7 8 9 10 SYNC SCLK D IN AV DD V /V REFIN REFOUT DAC7562, DAC7563, DAC8162 DAC8163, DAC8562, DAC8563 SLAS719E – AUGUST 2010 – REVISED JUNE 2015 www.ti.com 6 Pin Configuration and Functions 10-Pin VSSOP 10-Pin WSON With Thermal Pad DGS Package DSC Package (Top View) (Top View) (1) TI recommends connecting the thermal pad to the ground plane for better thermal dissipation. Pin Functions PIN I/O DESCRIPTION NAME NO. AVDD 9 I Power-supply input, 2.7 V to 5.5 V Asynchronous clear input. The CLR input is falling-edge sensitive. On activation of CLR, zero scale (DACxx62) or mid-scale (DACxx63) is loaded to all input and DAC registers. This sets the CLR 5 I DAC output voltages accordingly. The device exits clear code mode on the 24th falling edge of the next write to the device. Activating CLR during a write sequence aborts the write. Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the DIN 8 I serial clock input. Schmitt-trigger logic input GND 3 — Ground reference point for all circuitry on the device In synchronous mode, data update occurs with the falling edge of the 24th SCLK cycle, which follows a falling edge of SYNC. Such synchronous updates do not require the LDAC, which must be connected to GND permanently or asserted and held low before sending commands to the device. LDAC 4 I In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous DAC updates. Multiple single-channel commands can be written in order to set different channel buffers to desired values and then make a falling edge on the LDAC pin to update the DAC output registers simultaneously. SCLK 7 I Serial clock input. Data can be transferred at rates up to 50 MHz. Schmitt-trigger logic input Level-triggered control input (active-low). This input is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output updates following the 24th clock falling edge. If SYNC 6 I SYNC is taken high before the 23rd clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC756x, DAC816x, and DAC856x devices. Schmitt-trigger logic input VOUTA 1 O Analog output voltage from DAC-A VOUTB 2 O Analog output voltage from DAC-B VREFIN/VREFOUT 10 I/O Bidirectional voltage reference pin. If internal reference is used, 2.5-V output. 4 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DAC7562 DAC7563 DAC8162 DAC8163 DAC8562 DAC8563 |
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