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ADC12D1600RFIUT Datasheet(PDF) 50 Page - Texas Instruments |
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ADC12D1600RFIUT Datasheet(HTML) 50 Page - Texas Instruments |
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50 / 84 page  ADC12D1000RF, ADC12D1600RF SNAS519H – JULY 2011 – REVISED AUGUST 2015 www.ti.com 5.6 Register Maps Eleven read/write registers provide several control and configuration options in the Extended Control Mode. These registers have no effect when the device is in the Non-extended Control Mode. Each register description below also shows the Power-On Reset (POR) state of each control bit. See Table 5-9 for a summary. Table 5-9. Register Addresses A3 A2 A1 A0 HEX REGISTER ADDRESSED 0 0 0 0 0h Configuration Register 1 0 0 0 1 1h Reserved 0 0 1 0 2h I-channel Offset Adjust 0 0 1 1 3h I-channel Full-Scale Range Adjust 0 1 0 0 4h Calibration Adjust 0 1 0 1 5h Calibration Values 0 1 1 0 6h Reserved 0 1 1 1 7h DES Timing Adjust 1 0 0 0 8h Reserved 1 0 0 1 9h Reserved 1 0 1 0 Ah Q-channel Offset Adjust 1 0 1 1 Bh Q-channel Full-Scale Range Adjust 1 1 0 0 Ch Aperture Delay Coarse Adjust 1 1 0 1 Dh Aperture Delay Fine Adjust 1 1 1 0 Eh AutoSync 1 1 1 1 Fh Reserved Table 5-10. Configuration Register 1 Addr: 0h (0000b) POR state: 2000h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CAL DPS OVS TPM PDI PDQ Res LFS DES DEQ DIQ 2SC TSE SDR Res POR 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 CAL: Calibration Enable. When this bit is set to 1b, an on-command calibration is initiated. This bit is not reset automatically upon completion of the calibration. Therefore, the user must reset this bit to 0b and then set it to 1b again to execute another calibration. This bit is logically OR'd with the CAL Pin; both bit and pin must be set to 0b before either is used to execute a calibration. Bit 14 DPS: DCLK Phase Select. In DDR, set this bit to 0b to select the 0° Mode DDR Data-to-DCLK phase relationship and to 1b to select the 90° Mode. In SDR, set this bit to 0b to transition the data on the Rising edge of DCLK; set this bit to 1b to transition the data on the Falling edge of DCLK. (1) Bit 13 OVS: Output Voltage Select. This bit sets the differential voltage level for the LVDS outputs including Data, OR, and DCLK. 0b selects the lower level and 1b selects the higher level. See VOD in Electrical Characteristics: Digital Control and Output Pin for details. Bit 12 TPM: Test Pattern Mode. When this bit is set to 1b, the device will continually output a fixed digital pattern at the digital Data and OR outputs. When set to 0b, the device will continually output the converted signal, which was present at the analog inputs. See Test Pattern Mode for details about the TPM pattern. Bit 11 PDI: Power-down I-channel. When this bit is set to 0b, the I-channel is fully operational; when it is set to 1b, the I-channel is powered-down. The I-channel may be powered-down through this bit or the PDI Pin, which is active, even in ECM. Bit 10 PDQ: Power-down Q-channel. When this bit is set to 0b, the Q-channel is fully operational; when it is set to 1b, the Q-channel is powered down. The Q-channel may be powered down through this bit or the PDQ Pin, which is active, even in ECM. Bit 9 Reserved. Must be set as shown. Bit 8 LFS: Low-Frequency Select. If the sampling clock (CLK) is at or below 300 MHz, set this bit to 1b for improved performance. Bit 7 DES: Dual-Edge Sampling Mode select. When this bit is set to 0b, the device will operate in the Non-DES Mode; when it is set to 1b, the device will operate in the DES Mode. See DES/Non-DES Mode for more information. (1) This pin and bit functionality is not tested in production test; performance is tested in the specified and default mode only. 50 Detailed Description Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC12D1000RF ADC12D1600RF |
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