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ADC12D1000 Datasheet(PDF) 55 Page - Texas Instruments |
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ADC12D1000 Datasheet(HTML) 55 Page - Texas Instruments |
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55 / 86 page  ADC12D1000, ADC12D1600 www.ti.com SNAS480N – MAY 2010 – REVISED AUGUST 2015 Table 11. I-Channel Offset Adjust Addr: 2h (0010b) POR state: 0000h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Res OS OM(11:0) POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15:13 Reserved. Must be set to 0b. Bit 12 OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting this bet to 1b incurs a negative offset of the set magnitude. Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of approximately 11 µV. Monotonicity is ensured by design only for the 9 MSBs. Code Offset [mV] 0000 0000 0000 (default) 0 1000 0000 0000 22.5 1111 1111 1111 45 Table 12. I-Channel Full Scale Range Adjust Addr: 3h (0011b) POR state: 4000h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Res FM(14:0) POR 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 Reserved. Must be set to 0b. Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from 600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is ensured by design only for the 9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR values is available in ECM, that is, FSR values above 800 mV. See VIN_FSR in Electrical Characteristics: Analog Input/Output and Reference for characterization details. Code FSR [mV] 000 0000 0000 0000 600 100 0000 0000 0000 (default) 800 111 1111 1111 1111 1000 Table 13. Calibration Adjust Addr: 4h (0100b) POR state: DF4Bh Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Res CSS Res SSC Res POR 1 1 0 1 1 1 1 1 0 1 0 0 1 0 1 1 Bit 15 Reserved. Must be set as shown. Bit 14 CSS: Calibration Sequence Select. The default 1b selects the following calibration sequence: reset all previously calibrated elements to nominal values, do RIN Calibration, do internal linearity Calibration. Setting CSS = 0b selects the following calibration sequence: do not reset RIN to its nominal value, skip RIN calibration, do internal linearity Calibration. The calibration must be completed at least one time with CSS = 1b to calibrate RIN. Subsequent calibrations may be run with CSS = 0b (skip RIN calibration) or 1b (full RIN and internal linearity Calibration). Bits 13:8 Reserved. Must be set as shown. Bit 7 SSC: SPI Scan Control. Setting this control bit to 1b allows the calibration values, stored in Addr: 5h, to be read/written. When not reading/writing the calibration values, this control bit should left at its default 0b setting. See Calibration Feature for more information. Bits 6:0 Reserved. Must be set as shown. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 55 Product Folder Links: ADC12D1000 ADC12D1600 |
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