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ADC12D1000 Datasheet(PDF) 49 Page - Texas Instruments |
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ADC12D1000 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 86 page  ADC12D1000, ADC12D1600 www.ti.com SNAS480N – MAY 2010 – REVISED AUGUST 2015 7.5.1.1.1 Dual Edge Sampling Pin (DES) The Dual Edge Sampling (DES) Pin selects whether the ADC12D1x00 is in DES Mode (logic-high) or Non-DES Mode (logic-low). DES Mode means that a single analog input is sampled by both I- and Q-channels in a time- interleaved manner. One of the ADCs samples the input signal on the rising sampling clock edge (duty cycle corrected); the other ADC samples the input signal on the falling sampling clock edge (duty cycle corrected). In Non-ECM, only the I-input may be used for DES Mode, a.k.a. DESI Mode. In ECM, the Q-input may be selected through the DEQ Bit (Addr: 0h, Bit: 6), a.k.a. DESQ Mode. In ECM, both the I- and Q-inputs may be selected, a.k.a. DESIQ Mode. To use this feature in ECM, use the DES bit in the Configuration Register (Addr: 0h; Bit: 7). See DES/Non-DES Mode for more information. 7.5.1.1.2 Non-Demultiplexed Mode Pin (NDM) The Non-Demultiplexed Mode (NDM) Pin selects whether the ADC12D1x00 is in Demux Mode (logic-low) or Non-Demux Mode (logic-high). In Non-Demux Mode, the data from the input is produced at the sampled rate at a single 12-bit output bus. In Demux Mode, the data from the input is produced at half the sampled rate at twice the number of output buses. For Non-DES Mode, each I- or Q-channel will produce its data on one or two buses for Non-Demux or Demux Mode, respectively. For DES Mode, the selected channel will produce its data on two or four buses for Non-Demux or Demux Mode, respectively. This feature is pin-controlled only and remains active during both Non-ECM and ECM. See Demux/Non-Demux Mode for more information. 7.5.1.1.3 Dual Data Rate Phase Pin (DDRPH) The Dual Data Rate Phase (DDRPh) Pin selects whether the ADC12D1x00 is in 0° Mode (logic-low) or 90° Mode (logic-high). The Data is always produced in DDR Mode on the ADC12D1x00. The Data may transition either with the DCLK transition (0° Mode) or halfway between DCLK transitions (90° Mode). The DDRPh Pin selects 0° Mode or 90° Mode for both the I-channel: DI- and DId-to-DCLKI phase relationship and for the Q-channel: DQ- and DQd-to-DCLKQ phase relationship. To use this feature in ECM, use the DPS bit in the Configuration Register (Addr: 0h; Bit: 14). See DDR Clock Phase for more information. 7.5.1.1.4 Calibration Pin (CAL) The Calibration (CAL) Pin may be used to execute an on-command calibration or to disable the power-on calibration. The effect of calibration is to maximize the dynamic performance. To initiate an on-command calibration through the CAL pin, bring the CAL pin high for a minimum of tCAL_H input clock cycles after it has been low for a minimum of tCAL_L input clock cycles. Holding the CAL pin high upon power-on will prevent execution of the power-on calibration. In ECM, this pin remains active and is logically OR'd with the CAL bit. To use this feature in ECM, use the CAL bit in the Configuration Register (Addr: 0h; Bit: 15). See Calibration Feature for more information. 7.5.1.1.5 Calibration Delay Pin (CALDLY) The Calibration Delay (CalDly) Pin selects whether a shorter or longer delay time is present, after the application of power, until the start of the power-on calibration. The actual delay time is specified as tCalDly and may be found in Timing Requirements: Calibration. This feature is pin-controlled only and remains active in ECM. TI recommends selecting the desired delay time before power-on and not dynamically alter this selection. See Calibration Feature for more information. 7.5.1.1.6 Power-Down I-Channel Pin (PDI) The Power-Down I-channel (PDI) Pin selects whether the I-channel is powered down (logic-high) or active (logic- low). The digital data output pins, DI and DId, (both positive and negative) are put into a high impedance state when the I-channel is powered down. Upon return to the active state, the pipeline will contain meaningless information and must be flushed. The supply currents (typicals and limits) are available for the I-channel powered down or active and may be found in Electrical Characteristics: Power Supply. The device should be recalibrated following a power-cycle of PDI (or PDQ). Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Links: ADC12D1000 ADC12D1600 |
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