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RPC564L60L5BOSY Datasheet(PDF) 16 Page - STMicroelectronics

Part # RPC564L60L5BOSY
Description  microcontroller for Aerospace and Defense, SIL3/ASILD safety applications
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

RPC564L60L5BOSY Datasheet(HTML) 16 Page - STMicroelectronics

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Introduction
RPC56EL60L5
16/137
DocID026934 Rev 1
The SRAM module provides the following features:
System SRAM: 128 KB
ECC on 32-bit word (syndrome of 7 bits)
ECC covers SRAM bus address
1-bit error correction, 2-bit error detection
Wait states:
1 wait state for frequencies =< 120 MHz
0 wait states for frequencies =< 80 MHz
1.5.7
Platform flash memory controller
The following list summarizes the key features of the flash memory controller:
Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned
reads within the 32-bit container are supported. Only aligned word writes are
supported.
Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each
bank.
Code flash (bank0) interface provides configurable read buffering and page prefetch
support.
Four page-read buffers (each 128 bits wide) and a prefetch controller support
speculative reading and optimized flash access.
Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The
buffers implement a least-recently-used replacement algorithm to maximize
performance.
Programmable response for read-while-write sequences including support for stall-
while-write, optional stall notification interrupt, optional flash operation abort , and
optional abort notification interrupt.
Separate and independent configurable access timing (on a per bank basis) to support
use across a wide range of platforms and frequencies.
Support of address-based read access timing for emulation of other memory types.
Support for reporting of single- and multi-bit error events.
Typical operating configuration loaded into programming model by system reset.
The platform flash controller is replicated for each processor.
1.5.8
Platform Static RAM Controller (SRAMC)
The SRAMC module is the platform SRAM array controller, with integrated error detection
and correction.
The main features of the SRAMC provide connectivity for the following interfaces:
XBAR Slave Port (64-bit data path)
ECSM (ECC Error Reporting, error injection and configuration)
SRAM array


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