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LAN9730I Datasheet(PDF) 5 Page - Microchip Technology |
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LAN9730I Datasheet(HTML) 5 Page - Microchip Technology |
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5 / 222 page  2012-2015 Microchip Technology Inc. DS00001946A-page 5 LAN9730/LAN9730i 1.0 INTRODUCTION 1.1 General Terms Byte 8 bits CSR Control and Status Registers DWORD 32 bits FCT FIFO Controller FIFO First In First Out buffer Frame In the context of this document, a frame refers to transfers on the Ethernet interface. FSM Finite State Machine GPIO General Purpose I/O HSIC High-Speed Inter-Chip Host External system (includes processor, application software, etc.) Level-Triggered Sticky Bit This type of status bit is set whenever the condition that it represents is asserted. The bit remains set until the condition is no longer true and the sta- tus bit is cleared by writing a zero. LFSR Linear Feedback Shift Register MAC Media Access Controller MII Media Independent Interface N/A Not Applicable Packet In the context of this document, a packet refers to transfers on the USB inter- face. POR Power on Reset RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must always be zero for write operations. Unless otherwise noted, values are not ensured when reading reserved bits. Unless otherwise noted, do not read or write to reserved addresses. SCSR System Control and Status Register SMI Serial Management Interface TLI Transaction Layer Interface URX USB Bulk-Out Packet Receiver UTX USB Bulk-In Packet Transmitter WORD 16 bits ZLP Zero Length USB Packet |
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