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LAN8820 Datasheet(PDF) 7 Page - Microchip Technology |
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LAN8820 Datasheet(HTML) 7 Page - Microchip Technology |
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7 / 83 page  2009-2015 Microchip Technology Inc. DS00001871B-page 7 LAN8820/LAN8820I TABLE 2-2: SERIAL MANAGEMENT INTERFACE (SMI) PINS Num Pins Name Symbols Buffer Type Description 1 SMI Clock MDC IS (PD) Serial Management Interface clock. 1 SMI Data Input/ Output MDIO IS/O8 (PU) Serial Management Interface data input/output. TABLE 2-3: LED & CONFIGURATION PINS Num Pins Name Symbols Buffer Type Description 1 10BASE-T Link LED Indicator 10_LED O8 10BASE-T LED link indication. Refer to Section 3.9.1, "LEDs," on page 27 for additional information. 1 100BASE-TX Link LED Indicator 100_LED O8 100BASE-TX LED link indication. Refer to Section 3.9.1, "LEDs," on page 27 for additional information. Hardware Power Down (HPD) Mode Configuration Strap HPD_MODE IS (PD) This configuration strap is used to select the Hardware Power Down (HPD) mode. When pulled- up, the PLL is not disabled when HPD is asserted. When pulled-down, the PLL is disabled when HPD is asserted. Refer to Section 3.7.3, "Hardware Power-Down," on page 23 for additional information. See Note 2-2 for more information on configuration straps. 1 1000BASE-T Link LED Indicator 1000_LED O8 1000BASE-T LED link indication. Refer to Section 3.9.1, "LEDs," on page 27 for additional information. RGMII ID Mode Enable Configuration Strap RGMII_ID_MODE IS (PD) This configuration strap is used to configure the RGMII PHY TXC/RXC delay enable bit defaults. When pulled-up, the RGMII PHY TXC/RXC delays are enabled by default. When pulled-down, the RGMII PHY TXC/RXC delays are disabled be default. Refer to Section 3.3, "RGMII Interface," on page 18 for more information. See Note 2-2 for more information on configuration straps. 1 Configuration Input 0 CONFIG0 IS (PD) This pin sets the PHYADD[1:0] bits of the 10/100 Special Modes Register on reset or power-up. It must be connected to VSS, 100_LED, 1000_LED, or VDD25IO. Refer to Section 3.8.1.2, "CONFIG[3:0] Configuration Pins," on page 24 for additional information. 1 Configuration Input 1 CONFIG1 IS (PD) This pin sets the PAUSE bit of the Auto Negotiation Advertisement Register and PHYADD [2] bit of the 10/100 Special Modes Register on reset or power- up. It must be connected to VSS, 100_LED, 1000_LED, or VDD25IO. Refer to Section 3.8.1.2, "CONFIG[3:0] Configuration Pins," on page 24 for additional information. |
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Similar Description - LAN8820 |
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