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LAN8820 Datasheet(PDF) 23 Page - Microchip Technology |
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LAN8820 Datasheet(HTML) 23 Page - Microchip Technology |
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23 / 83 page  2009-2015 Microchip Technology Inc. DS00001871B-page 23 LAN8820/LAN8820I 3.6.3 POWER-DOWN RESET A power-down reset is automatically activated when the device comes out of the power-down mode. During power- down, the registers are not reset. Configuration straps and CONFIG[3:0] pins are not latched as a result of a power- down reset. The power-down reset is internally extended by 256 s after exiting the power-down mode to allow the PLLs to stabilize before the logic is released from reset. Refer to Section 3.7, "Power-Down modes," on page 23 for details on the various power-down modes. 3.7 Power-Down modes The device supports 3 power-down modes: • General Power-Down • Energy Detect Power-Down • Hardware Power-Down 3.7.1 GENERAL POWER-DOWN This power-down mode is controlled by the Power Down bit of the Basic Control Register. In this mode, the entire device is powered-down except for the serial management interface. The device remains in the general power-down mode while Power Down is set. When Power Down is cleared, the device powers up and is automatically reset (via a Power- Down Reset). For maximum power savings, auto-negotiation should be disabled before enabling the general power- down mode. 3.7.2 ENERGY DETECT POWER-DOWN This power-down mode is controlled by the EDPWRDOWN bit of the 10/100 Mode Control/Status Register. In this mode, when no energy is present on the line, nothing is transmitted and the device is powered-down except for the manage- ment interface, the SQUELCH circuit and the ENERGYON logic. The ENERGYON bit in the 10/100 Mode Control/Status Register is asserted when there is valid energy from the line (100BASE-TX, 10BASE-T, or Auto-Negotiation signals) and the PHY powers-up. It automatically resets itself into the previous state prior to power-down, and stays in active mode as long as energy exists on the line. If the ENGERGYON interrupt is enabled (INT7_EN of the Interrupt Mask Register), IRQ is asserted. 3.7.3 HARDWARE POWER-DOWN This power-down mode is controlled by the HPD pin. In this mode, the entire device is powered-down except for the serial management interface. The HPD_MODE configuration strap selects whether the PLL will be shut down when in hardware power-down mode. To exit the hardware power-down mode, the HPD pin must be deasserted, followed by the deassertion of the Power Down bit in the Basic Control Register. If the hardware power-down mode is set to shut down the PLL, a software reset must also be issued. Note 1: The device will wake-up in the hardware power-down mode if the HPD pin is asserted during hardware reset. 2: For additional information on the HPD_MODE configuration strap, refer to Section 3.8.1.1, "Configuration Straps," on page 24. 3.8 Configuration The device mode of operation may be controlled by hardware and software (register-selectable) configuration options. The initial configuration may be selected in hardware as described in Section 3.8.1. In addition, register-selectable soft- ware configuration options may be used to further define the functionality of the transceiver as described in Section 3.8.2. The device supports both IEEE 802.3-2005 compliant and vendor-specific register functions. 3.8.1 HARDWARE CONFIGURATION Hardware configuration is controlled via multiple configuration straps and the CONFIG[3:0] configuration pins. These items are detailed in the following sub-sections. Note: The first and possibly second packet to activate ENERGYON may be lost. |
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