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LAN8710A Datasheet(PDF) 31 Page - Microchip Technology |
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LAN8710A Datasheet(HTML) 31 Page - Microchip Technology |
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31 / 82 page  Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology Datasheet SMSC LAN8710A/LAN8710Ai 31 Revision 1.4 (08-23-12) DATASHEET carrier sense - CRS_DV Reference Clock - (RMII references usually define this signal as REF_CLK) 3.4.2.1 CRS_DV - Carrier Sense/Receive Data Valid The CRS_DV is asserted by the device when the receive medium is non-idle. CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. In 10BASE- T mode when squelch is passed, or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are detected, the carrier is said to be detected. Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which presents the first di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted only on nibble boundaries). If the device has additional bits to be presented on RXD[1:0] following the initial deassertion of CRS_DV, then the device shall assert CRS_DV on cycles of REF_CLK which present the second di-bit of each nibble and de-assert CRS_DV on cycles of REF_CLK which present the first di-bit of a nibble. The result is, starting on nibble boundaries, CRS_DV toggles at 25 MHz in 100Mbps mode and 2.5 MHz in 10Mbps mode when CRS ends before RXDV (i.e. the FIFO still has bits to transfer when the carrier event ends). Therefore, the MAC can accurately recover RXDV and CRS. During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal decoding takes place. 3.4.2.2 Reference Clock (REF_CLK) The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0], TXEN, TXD[1:0] and RXER. The device uses REF_CLK as the network clock such that no buffering is required on the transmit data path. However, on the receive data path, the receiver recovers the clock from the incoming data stream, and the device uses elasticity buffering to accommodate for differences between the recovered clock and the local REF_CLK. 3.4.3 MII vs. RMII Configuration The device must be configured to support the MII or RMII bus for connectivity to the MAC. This configuration is done via the RMIISEL configuration strap. MII or RMII mode selection is configured based on the strapping of the RMIISEL configuration strap as described in Section 3.7.3, "RMIISEL: MII/RMII Mode Configuration," on page 37. Most of the MII and RMII pins are multiplexed. Table 3.2, "MII/RMII Signal Mapping" describes the relationship of the related device pins to the MII and RMII mode signal names. |
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Similar Description - LAN8710A |
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