ADS7828-Q1

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SBAS456B – DECEMBER 2008 – REVISED JANUARY 2016

Switching Characteristics (continued)

(1)(2) See Figure 1.

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Standard mode

4

μs

Fast mode

600

High period of the SCL clock

60

ns

120

Standard mode

4.7

μs

Setup time for a repeated Start

Fast mode

600

condition

ns

High-speed mode

160

Standard mode

250

Data setup time

Fast mode

100

ns

High-speed mode

10

Standard mode

0

3.45

μs

Fast mode

0

0.9

Data hold time

0

82

ns

0

162

Standard mode

1000

Fast mode

300

Rise time of SCL signal

ns

10

40

20

80

Standard mode

1000

Rise time of SCL signal after a

Fast mode

300

repeated Start condition and after an

ns

10

80

acknowledge bit

20

160

Standard mode

300

Fast mode

300

Fall time of SCL signal

ns

10

40

20

80

Standard mode

1000

Fast mode

300

Rise time of SDA signal

ns

10

80

20

160

Standard mode

300

Fast mode

300

Fall time of SDA signal

ns

10

80

20

160

Standard mode

4

μs

Setup time for Stop condition

Fast mode

600

ns

High-speed mode

160

Capacitive load for SDA or SCL

400

pF

Fast mode

50

Pulse width of spike suppressed

ns

High-speed mode

10

Noise margin at the high level for

each connected device (including

V

hysteresis)

Noise margin at the low level for

each connected device (including

V

hysteresis)

(4)

signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.

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