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ADS7828-Q1 Datasheet(PDF) 10 Page - Texas Instruments |
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ADS7828-Q1 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 35 page ADS7828-Q1 SBAS456B – DECEMBER 2008 – REVISED JANUARY 2016 www.ti.com Electrical Characteristics for ADS7828EB (continued) +VDD = 5 V, VREF = External 5 V, SCL clock frequency = 3.4 MHz (high-speed mode), over operating free-air temperature range, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltage Reference Output VO Output voltage 2.475 2.5 2.525 V Internal reference drift 15 ppm/°C Internal reference on 110 Ω zo Output impedance Internal reference off 1 G Ω IQ Quiescent current 1300 µA Voltage Reference Input rI Input resistance 1 G Ω Current drain 20 µA Digital Input and Output VOL Low-level output voltage Minimum 3-mA sink current 0.4 V IIH High-level input current VIH = +VDD + 0.5 V 10 µA IIL Low-level input current VIL = –0.3 V –10 µA Power Supply High-speed mode: SCL = 3.4 MHz 750 1000 IQ Quiescent current Fast mode: SCL = 400 kHz 300 µA Standard mode: SCL = 100 kHz 150 High-speed mode: SCL = 3.4 MHz 3.75 5 PO Power dissipation Fast mode: SCL = 400 kHz 1.5 µW Standard mode: SCL = 100 kHz 0.75 High-speed mode: SCL = 3.4 MHz 400 Power-down current with wrong Fast mode: SCL = 400 kHz 150 µA address selected Standard mode: SCL = 100 kHz 35 IPD Full power-down current SCL pulled high, SDA pulled high 400 3000 nA 6.9 Switching Characteristics +VDD = 2.7 V, over operating free-air temperature range, unless otherwise noted. (1) (2) See Figure 1. PARAMETER TEST CONDITIONS MIN MAX UNIT Standard mode 100 kHz Fast mode 400 fSCL SCL clock frequency Cb = 100 pF max 3.4 High-speed mode MHz Cb = 400 pF max 1.7 Standard mode 4.7 Bus free time between Stop and tBUF μs Start conditions Fast mode 1.3 Standard mode 4 μs tHD; STA Hold time (repeated) Start condition Fast mode 600 ns High-speed mode 160 Standard mode 4.7 μs Fast mode 1.3 tlow Low period of the SCL clock Cb = 100 pF max 160 High-speed mode(3) ns Cb = 400 pF max 320 (1) All values referred to VIH(MIN) and VIL(MAX) levels. (2) Not production tested, except for the perameter tHD; DAT, data hold time, high-speed mode, Cb = 100 pF max. (3) For bus line loads (CB) between 100 pF and 400 pF, the timing parameters must be linearly interpolated. 10 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: ADS7828-Q1 |
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