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DLPR410YVA Datasheet(PDF) 9 Page - Texas Instruments |
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DLPR410YVA Datasheet(HTML) 9 Page - Texas Instruments |
9 / 18 page DLPR410 www.ti.com DLPS027D – AUGUST 2012 – REVISED JANUARY 2016 7.3 Feature Description 7.3.1 Data Interface 7.3.1.1 Data Outputs The DLPR410 is configured for serial mode operation, where D0 is the data output pin. D0 output pin provides a serial connection to the DLPC410, where the configuration is read out by the DLPC410. 7.3.1.2 Configuration Clock Input The configuration CLK is connected to the DLPC410 in master mode, where the DLPC410 provides the clock pulses to read the configuration from the DLPR410. 7.3.1.3 Output Enable and Reset When the OE/(RESET) input is held low, the address counter is reset and the Data and CLKOUT outputs are placed in high-impedance state. OE/(RESET) must be pulled High using an external 4.7-k Ω pull-up to VCCO. 7.3.1.4 Chip Enable The (CE) input is asserted by the DLPC410 to enable the Data and CLKOUT outputs. When (CE) is held high, the DLPR410 address counter is reset, and the Data and CLKOUT outputs are placed in high-impedance states. 7.3.1.5 Configuration Pulse The DLPR410 is configured in serial mode when the Configuration Pulse (CF) is held high and (CE) and OE are enabled. New data is available a short time after each rising clock edge. 7.3.1.6 Revision Selection REV_SEL_0, REV_SEL_1, and (EN_EXT_SEL) signals are used for selecting which revision to be the default. Setting all three signals to GND will default to revision 0 for simple DLPR410 setup. 7.4 Device Functional Modes To successfully program the DLPC410 upon power-up, the DLPR410 must be configured and connected to the DLPC410 as shown in Figure 1. Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DLPR410 |
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