1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CS

SCLK

V

A

DOUT

AGND

DIN

IN0

V

D

IN1

DGND

IN2

IN7

IN3

IN6

IN4

IN5

ADC128S022

ADC128S022

www.ti.com

SNAS334F – AUGUST 2005 – REVISED NOVEMBER 2015

5 Pin Configuration and Functions

PW Package

16-Pin TSSOP

Top View

Pin Functions

PIN

TYPE

DESCRIPTION

NAME

NO.

Chip select. On the falling edge of CS, a conversion process begins. Conversions continue

CS

1

Digital I/O

as long as CS is held low.

Positive analog supply pin. This voltage is also used as the reference voltage. This pin

Power

2

should be connected to a quiet +2.7-V to +5.25-V source and bypassed to GND with 1-µF

Supply

and 0.1-µF monolithic ceramic capacitors located within 1 cm of the power pin.

Power

AGND

3

The ground return for the analog supply and signals.

Supply

IN0 to IN7

4-11

Analog I/O

Power

DGND

12

The ground return for the digital supply and signals.

Supply

Power

13

bypassed to GND with a 0.1-µF monolithic ceramic capacitor located within 1 cm of the

Supply

power pin.

Digital data input. The ADC128S022's Control Register is loaded through this pin on rising

DIN

14

Digital I/O

edges of the SCLK pin.

Digital data output. The output samples are clocked out of this pin on the falling edges of

DOUT

15

Digital I/O

the SCLK pin.

Digital clock input. The specified performance range of frequencies for this input is 0.8 MHz

SCLK

16

Digital I/O

to 3.2 MHz. This clock directly controls the conversion and readout processes.

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