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DLP3010FQK Datasheet(PDF) 11 Page - Texas Instruments |
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DLP3010FQK Datasheet(HTML) 11 Page - Texas Instruments |
11 / 39 page 1.0 * VID VDCLK_P , VDCLK_N VD_P(0:7) , VD_N(0:7) 0.0 * VID VCM 0.2 * VID 0.8 * VID tf tr 0.0 * VDD 0.2 * VDD 0.3 * VDD 0.7 * VDD 0.8 * VDD 1.0 * VDD VIH(AC) VIH(DC) VIL(DC) VIL(AC) tf tr LS_CLK, LS_WDATA 0.0 * VDD 0.2 * VDD 0.8 * VDD 1.0 * VDD tf tr DMD_DEN_ARSTZ LS_ WDATA LS_CLK tw(H) tw(L) tc 50% 50% 50% 50% 50% th tsu twindow DLP3010 www.ti.com DLPS051A – SEPTEMBER 2014 – REVISED APRIL 2015 Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B. Figure 2. LPSDR Switching Parameters Figure 3. LPSDR Input Rise and Fall Slew Rate Figure 4. SubLVDS Input Rise and Fall Slew Rate Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DLP3010 |
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