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DLP2010NIR Datasheet(PDF) 3 Page - Texas Instruments |
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DLP2010NIR Datasheet(HTML) 3 Page - Texas Instruments |
3 / 39 page DLP2010NIR www.ti.com DLPS059A – MARCH 2015 – REVISED OCTOBER 2015 5 Pin Configuration and Functions FQJ Package 40-Pin CLGA Bottom View Pin Functions – Connector Pins(1) PIN PACKAGE NET TRACE TYPE SIGNAL DATA RATE DESCRIPTION LENGTH(2) (mm) NAME NO. DATA INPUTS, SUBLVDS INTERFACE D_N(0) G4 I SubLVDS Double Input Data Pair 0, Negative 7.03 D_P(0) G3 I SubLVDS Double Input Data Pair 0, Positive 7.03 D_N(1) G8 I SubLVDS Double Input Data Pair 1, Negative 7.03 D_P(1) G7 I SubLVDS Double Input Data Pair 1, Positive 7.03 D_N(2) H5 I SubLVDS Double Input Data Pair 2, Negative 7.02 D_P(2) H6 I SubLVDS Double Input Data Pair 2, Positive 7.02 (1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B. (2) Net trace lengths inside the package: Relative dielectric constant for the FQJ ceramic package is 9.8. Propagation speed = 11.8 / sqrt(9.8) = 3.769 inches/ns. Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DLP2010NIR |
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