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AN332 Datasheet(PDF) 88 Page - Silicon Laboratories

Part No. AN332
Description  Si47XX PROGRAMMING GUIDE
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

AN332 Datasheet(HTML) 88 Page - Silicon Laboratories

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AN332
88
Rev. 1.0
Property 0x0202. REFCLK_PRESCALE
Sets the number used by the prescaler to divide the external RCLK down to the internal REFCLK. The range may
be between 1 and 4095 in 1 unit steps. For example, an RCLK of 13 MHz would require a prescaler value of 400 to
divide it to 32500 Hz. The reference clock frequency property would then need to be set to 32500 Hz. The RCLK
must be valid 10 ns before sending and 20 ns after completing the FM_TUNE_FREQ and FM_TUNE_START
commands. In addition, the RCLK must be valid at all times for proper AFC operation. The RCLK may be removed
or reconfigured at other times. The CTS bit (and optional interrupt) is set when it is safe to send the next command.
This property may only be set or read when in powerup mode. The default is 1.
Available in: All
Default: 0x0001
Step: 1
Range: 1–4095
Bit
D15
D14
D13
D12
D11
D10
D9
D8D7D6D5D4D3D2D1D0
Name
00
0
RCLK
SEL
REFCLKP[11:0]
Bit
Name
Function
15:13
Reserved
Always write to 0.
12
RCLKSEL
RCLKSEL.
0 = RCLK pin is clock source.
1 = DCLK pin is clock source.
11:0
REFCLKP[11:0]
Prescaler for Reference Clock.
Integer number used to divide clock frequency down to REFCLK frequency. The
allowed REFCLK frequency range is between 31130 and 34406 Hz (32768 5%), or
0 (to disable AFC).


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