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LMK00338 Datasheet(PDF) 15 Page - Texas Instruments

Part No. LMK00338
Description  8-Output Differential Clock Buffer/Level Translator
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LMK00338 Datasheet(HTML) 15 Page - Texas Instruments

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MAC
PCI Express®
PHY
E.g.: XIO1100
PCI Express®
fan-out switch
E.g.: XIO3130
PCI Express®
bridge
E.g.: XIO2000A
FPGA with
PCI Express®
Core
Fan Out Buffer
E.g.: LMK00338
100MHz
Reference
Oscillator
Add-In Card
Mainboard
Connector
PCI Express®
bridge
E.g.: XIO2000A
Add-In Card
PCI Express®
bridge
E.g.: XIO2000A
Add-In Card
PCI Express®
device
Add-In Card
Data
Clock
LMK00338
www.ti.com
SNAS636A – DECEMBER 2013 – REVISED OCTOBER 2014
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A common PCIe application, such as a server card, consists of several building blocks, which all need a
reference clock. In the mostly used Common RefClk architecture, the clock is distributed from a single source to
both RX and TX. This requires either a Clock generator with high output count or a buffer like the LMK00338.
The buffer simplifies the clocking tree and provides a cost and space optimized solution. While using a buffer to
distribute the clock, the additive jitter needs to be considered. The LMK00338 is an ultra-low additive jitter PCIe
clock buffer suitable for all current and future PCIe Generations.
9.2 Typical Applications
Figure 15. Example PCI Express Application Diagram
9.2.1 Design Requirements
9.2.1.1 Driving the Clock Inputs
The LMK00338 has two universal inputs (CLKin0/CLKin0* and CLKin1/CLKin1*) that can accept AC- or DC-
coupled 3.3V/2.5V LVPECL, LVDS, CML, SSTL, and other differential and single-ended signals that meet the
input requirements specified in the Electrical Characteristics. The device can accept a wide range of signals due
to its wide input common mode voltage range (VCM ) and input voltage swing (VID) / dynamic range. For 50% duty
cycle and DC-balanced signals, AC coupling may also be employed to shift the input signal to within the VCM
range. Refer to Termination and Use of Clock Drivers for signal interfacing and termination techniques.
Copyright © 2013–2014, Texas Instruments Incorporated
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Product Folder Links: LMK00338


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