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SI88643ED-IS Datasheet(PDF) 4 Page - Silicon Laboratories |
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SI88643ED-IS Datasheet(HTML) 4 Page - Silicon Laboratories |
4 / 48 page Si88x4x 4 Preliminary Rev. 0.6 Output Voltage Accuracy2 See Figure 2 ILOAD = 0 mA –5 — +5 % Line Regulation VOUT(line)/V DDP See Figure 2 ILOAD = 50 mA VDDP varies from 4.5 to 5.5 V 1mV/V Load Regulation VOUT(load)/V OUT See Figure 2 ILOAD = 50 to 400 mA 0.1 % Output Voltage Ripple Si8824x, Si8834x Si8844x, Si8864x ILOAD = 100 mA See Figure 2 See Figure 3 100 mV p-p Turn-on overshoot VOUT(start) See Figure 2 CIN = COUT = 0.1 μF in parallel with 10 μF, ILOAD = 0 A 2% Continuous Output Current Si8824x, Si8834x 5.0 V to 5.0 V 3.3 V to 3.3 V 3.3 V to 5.0 V 5.0 V to 3.3 V Si8844x, Si8864x 24.0 to 5.0 V 24.0 to 3.0 V ILOAD(max) See Figure 2 See Figure 3 400 400 250 550 1000 1500 mA Cycle-by-cycle average current limit Si8824x, Si8834x ILIM See Figure 2 Output short circuited 3A No Load Supply Current IDDP Si8824x, Si8834x IDDPQ_DCDC3 See Figure 2 VDDP = VDDA = 5 V 30 mA No Load Supply Current IDDA Si8824x, Si8834x IDDAQ_DCDC4 See Figure 2 VDDP = VDDA = 5 V 5.7 mA Table 2. Electrical Characteristics1 (Continued) VIN =24 V; VDDA = 4.3 V (see Figure 3) for all Si8844x/64x; VDDA =VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8824x/34x; TA = –40 to 125 °C unless otherwise noted Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Over recommended operating conditions as noted in Table 1. 2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset 3. VDDP current needed for dc-dc circuits. 4. VDDA current needed for dc-dc circuits. 5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output. |
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