Electronic Components Datasheet Search |
|
CDCP1803RGERG4 Datasheet(PDF) 3 Page - Texas Instruments |
|
CDCP1803RGERG4 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 25 page CDCP1803 www.ti.com SCAS727F – NOVEMBER 2003 – REVISED DECEMBER 2013 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. EN 1 I ENABLE: Enables or disables all outputs simultaneously. (with 60-k Ω pullup) EN = 1: outputs on according to S[2:0] settings EN = 0: outputs Y[2:0] off (high impedance) See Table 1 for details. IN, IN 3, 4 I (differential) Differential input clock. Input stage is sensitive and has a wide common-mode range. Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS, CML, HSTL). Because the input is high-impedance, it is recommended to terminate the PCB transmission line before the input (e.g., with 100 Ω across input). Input can also be driven by a single-ended signal if the complementary input is tied to VBB. A more- advanced scheme for single-ended signals is given in the Application Information section near the end of this document. The inputs employ an ESD structure protecting the inputs in case of an input voltage exceeding the rails by more than ~0.7 V. Reverse biasing of the IC through these inputs is possible and must be prevented by limiting the input voltage < VDD. NC 12 No connect. Leave this terminal open or tie to ground. S[2:0] 24, 19, 18 I Select mode of operation. Defines the output configuration of Y[2:0], see Table 1 for (with 60-k Ω pullup) configuration. VBB 6 O Bias voltage output can be used to bias unused complementary input IN for single- ended input signals. The output voltage of VBB is VDD – 1.3 V. When driving a load, the output current drive is limited to about 1.5 mA. VDDPECL 2, 5 Supply Supply voltage PECL input + internal logic VDD[2:0] 8, 11, 14, Supply PECL output supply voltage for output Y[2:0]. Each output can be disabled by pulling 17, 20, 23 the corresponding VDDx to GND. CAUTION: In this mode, no voltage from outside may be forced, because internal diodes could be forced in forward direction. Thus, it is recommended to disconnect the output if it is not being used. VSS 7, 13 Supply Device ground Y[2:0] 9, 15, 21 O (LVPECL) LVPECL clock outputs. These outputs provide low-skew copies of IN or down-divided Y[2:0] 10, 16, 22 copies of clock IN based on selected mode of operation S[2:0]. If an output is unused, the output can simply be left open to save power and minimize noise impact to the remaining outputs. Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links :CDCP1803 |
Similar Part No. - CDCP1803RGERG4 |
|
Similar Description - CDCP1803RGERG4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |