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CDCM7005 Datasheet(PDF) 18 Page - Texas Instruments

Part # CDCM7005
Description  3.3-V High Performance Clock Synchronizer and Jitter Cleaner
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM7005 Datasheet(HTML) 18 Page - Texas Instruments

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background image
T0064-01
t
(lockdetect)
SelectedREFatPFD
(clockfedthroughMDividerandMDelay)
VCXO_INatPFD
(clockfedthroughNDividerandNDelay)
CDCM7005
SCAS793F – JUNE 2005 – REVISED JULY 2015
www.ti.com
Feature Description (continued)
9.3.2.1 PLL Lock/Out-of-Lock Definition
The PLL is locked (set high), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and
Feedback Clock (VCXO_IN clock) at the PFD (phase frequency detect) are inside a predefined lock detect
window, or if no frequency offset appears, for a pre-defined number of successive clock cycles.
The PLL is out-of-lock (set low), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and
Feedback Clock (VCXO_IN clock) at the PFD are outside the predefined lock detect window or if a frequency
offset appears.
Both, the lock detect window and the number of successive clock cycles are user definable (Word 3, Bit 2-6).
Figure 16. Lock Detect Window
The lock detect window describes the maximum allowed time difference for lock detect between the rising edge
of PRI_REF or SEC_REF and VCXO_IN. The time difference is detected at the phase frequency detector. The
rising edge of PRI_REF or SEC_REF is taken as reference. The rising edge of VCXO_IN is outside the lock
detect window if there is a phase displacement of more than +0.5 × t(lockdetect) or -0.5 x t(lockdetect).
18
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