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CDCM6208V1FRGZR Datasheet(PDF) 14 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 14 Page - Texas Instruments

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CDCM6208V1F
SCAS943 – MAY 2015
www.ti.com
8.17
LVDS (Low-Power CML) Output Characteristics
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135V to
3.465V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fOUT-I
Integer output divider
1.55
400
MHz
Output frequency
fOUT-F
Fractional output divider
0.78
400
MHz
fACC-F
Output frequency error (1)
Fractional output divider
-1
1
ppm
Output AC coupled
VCM-AC
AC coupled with 50
Ω receiver termination
VDD_Yx_Yy – 0.76
V
common mode voltage
Output DC coupled
VCM-DC
DC coupled with 50
Ω on-chip termination to VDD_Yx_Yy
VDD_Yx_Yy – 0.13
V
common mode voltage
|VOD|
Differential output voltage
100
Ω diff load AC coupling, (See Figure 12)
0.247
0.34
0.454
V
Differential output peak-to-
VOUT
2 x |VOD|
V
peak voltage
tR/tF
Output rise/fall time
±100mV around crossing point
300
ps
VDD_Yx = 1.8 V
–159.3
–154.5
dBc/Hz
PN-floor
Phase noise floor
fOUT= 122.88 MHz
VDD_Yx = 2.5/3.3 V
–159.1
–154.9
dBc/Hz
Y[3:0]
47.5%
52.5%
ODC
Output duty cycle
Not in bypass mode
Y[7:4]
45%
55%
ROUT
Output impedance
Measured from pin to VDD_Yx_Yy
167
Ω
(1)
The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach
of a multiple of 1 over 220, the actual output frequency error is 0.
8.18
HCSL Output Characteristics
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 to 1.89 V, 2.375 V to 2.625 V,3.135 V to 3.465 V,
TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fOUT-I
Integer Output Divider
1.55
400
MHz
Output frequency
fOUT-F
Fractional Output Divider
0.78
400
MHz
fACC-F
Output Frequency Error (1)
Fractional Output Divider
-1
1
ppm
VDD_Yx_Yy = 2.5/3.3 V
0.2
0.34
0.55
V
VCM
Output Common Mode Voltage
VDD_Yx_Yy = 1.8 V
0.2
0.33
0.55
V
VDD_Yx_Yy = 2.5/3.3 V
0.4
0.67
1.0
V
|VOD|
Differential Output Voltage
VDD_Yx_Yy = 1.8 V
0.4
0.65
1.0
V
VDD_Yx_Yy = 2.5/3.3 V
1.0
2.1
V
Differential Output Peak-to-peak
VOUT
Voltage
VDD_Yx_Yy = 1.8 V
2 x|VOD|
V
Measured from VDIFF= –100 mV to
100
167
250
VDIFF = +100mV, VDD_Yx_Yy = 2.5/3.3 V
tR/tF
Output Rise/Fall Time
ps
Measured from VDIFF= –100 mV to
120
192
295
VDIFF= +100 mV, VDD_Yx_Yy = 1.8 V
VDD_Yx_Yy = 1.8 V
–158.8
–153
dBc/Hz
PN-floor
Phase Noise Floor
fOUT = 122.88 MHz
VDD_Yx = 2.5/3.3 V
–157.6
–153
dBc/Hz
ODC
Output Duty Cycle
Not in bypass mode
45%
55%
(1)
The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach
of A 1/220 multiple, the actual output frequency error is 0.
14
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Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: CDCM6208V1F


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