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CDCM6208V1FRGZR Datasheet(PDF) 7 Page - Texas Instruments

Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 7 Page - Texas Instruments

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CDCM6208V1F
www.ti.com
SCAS943 – MAY 2015
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD_Yx_Yy
Output Supply Voltage
1.71
1.8/2.5/3.3
3.465
V
VDD_PLL1
Core Analog Supply Voltage
1.71
1.8/2.5/3.3
3.465
V
VDD_PLL2
DVDD
Core Digital Supply Voltage
1.71
1.8/2.5/3.3
3.465
V
VDD_PRI,
Reference Input Supply Voltage
1.71
1.8/2.5/3.3
3.465
V
VDD_SEC
VDD power-up ramp time (0 to 3.3 V) PDN left open, all VDD tight
ΔVDD/Δt
50 < tPDN
ms
together PDN low-high is delayed (1)
TA
Ambient Temperature
-40
85
°C
SDA and SCL in I 2 C MODE (SI_MODE[1:0] = 01)
DVDD = 1.8 V
–0.5
2.45
V
VI
Input Voltage
DVDD = 3.3 V
–0.5
3.965
V
100
dR
Data Rate
kbps
400
0.7 x
VIH
High-level input voltage
V
DVDD
VIL
Low-level input voltage
0.3 x DVDD
V
CBUS_I2C
Total capacitive load for each bus line
400
pF
(1)
For fast power up ramps under 50 ms and when all supply pins are driven from the same power supply source, PDN can be left floating.
For slower power up ramps or if supply pins are sequenced with uncertain time delays, PDN needs to be held low until DVDD,
VDD_PLLx, and VDD_PRI/SEC reach at least 1.45V supply voltage. See application section on mixing power supplies and particularly
Figure 58 for details.
8.4 Thermal Information, Airflow = 0 LFM
(1) (2) (3) (4)
CDCM6208
THERMAL METRIC(1)
RGZ
UNIT
48 PINS VQFN
RθJA
Junction-to-ambient thermal resistance
30.27
RθJC(top)
Junction-to-case (top) thermal resistance
16.58
RθJB
Junction-to-board thermal resistance
6.83
°C/W
ψJT
Junction-to-top characterization parameter
0.23
ψJB
Junction-to-board characterization parameter
6.8
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.06
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
(3)
Connected to GND with 36 thermal vias (0.3 mm diameter).
(4)
θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.
Copyright © 2015, Texas Instruments Incorporated
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