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CDCM6208V1FRGZR Datasheet(PDF) 67 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 67 Page - Texas Instruments

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De-Serializer
Serializer
TX REF
CLOCK
TX PLL
serial data with
embedded clock
CDR
RX REF
CLOCK
fhigh=BWTX PLL
RX PLL
flow=BWRX PLL
fhigh
flow
HTransfer(f) = HTXPLL * ( 1 - HRXPLL)
flow=1.875MHz for 10GbE
fhigh=20MHz for 10GbE
CDCM6208V1F
www.ti.com
SCAS943 – MAY 2015
11.2.2 Detailed Design Procedure
11.2.2.1 Jitter Considerations in SERDES Systems
The most jitter sensitive application besides driving A-to-D converters are systems deploying a serial link using
Serializer and De-serializer implementation (for example, 10 GigEthernet). Fully estimating the clock jitter impact
on the link budget requires an understanding of the transmit PLL bandwidth and the receiver CDR bandwidth. As
can be seen in Figure 50, the bandwidth of TX and RX is the frequency range in which clock jitter adds without
any attenuation to the jitter budget of the link. Outside of these frequencies, the SERDES link will attenuate clock
jitter with a 20 dB/dec or even steeper roll-off.
Figure 50. Serial Link Jitter Budget Explanation
Example: SERDES link with KeyStone™ I DSP
The SERDES TX PLL of the TI KeyStone™ I DSP family (see SPRABI2) for the SRIO interface, has a 13 MHz
PLL bandwidth (Low Pass Characteristic, see Figure 50). The CDCM6208V2, pin-mode 27, was characterized in
this example over Process, Voltage and Temperature (PVT) with a low pass filter of 13 MHz to simulate the TX
PLL. The attenuation is higher or equal to 20 dB/dec; therefore, the characterization used 20 dB/dec as worst
case.
Table 38 shows the maximum Total Jitter(1) over PVT with and without Low Pass Filter.
Table 38. Maximum Total Jitter Over PVT With and Without Low Pass Filter
MAX TJ [ps]
FREQUENCY
MAX TJ [ps]
MAX TJ [ps]
OUTPUT
with 13 MHz LOW PASS
[MHz]
DSP SPEC
without LOW PASS FILTER
FILTER
Y0
122.88
56
9.43
8.19
Y2
30.72
56
9.60
7.36
Y3
30.72
56
9.47
7.42
(1)
Input signal: 250fs RMS (Integration Range 12kHz to 5MHz)
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: CDCM6208V1F


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