Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

CDCM6208V1FRGZR Datasheet(PDF) 66 Page - Texas Instruments

Click here to check the latest version.
Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
Download  87 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 66 Page - Texas Instruments

Back Button CDCM6208V1FRGZR Datasheet HTML 62Page - Texas Instruments CDCM6208V1FRGZR Datasheet HTML 63Page - Texas Instruments CDCM6208V1FRGZR Datasheet HTML 64Page - Texas Instruments CDCM6208V1FRGZR Datasheet HTML 65Page - Texas Instruments CDCM6208V1FRGZR Datasheet HTML 66Page - Texas Instruments CDCM6208V1FRGZR Datasheet HTML 67Page - Texas Instruments CDCM6208V1FRGZR Datasheet HTML 68Page - Texas Instruments CDCM6208V1FRGZR Datasheet HTML 69Page - Texas Instruments CDCM6208V1FRGZR Datasheet HTML 70Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 66 / 87 page
background image
CDCM6208V1F
SCAS943 – MAY 2015
www.ti.com
11.2.1.16.6
Output MUX on Y4 and Y5
The CDCM6208V1F device outputs Y4 and Y5 can either be used as independent fractional outputs or allow
bypassing of the PLL in order to output the primary or secondary input signal directly.
11.2.1.16.7
Staggered CLK Output Powerup for Power Sequencing of a DSP
DSPs are sensitive to any kind of voltage swing on unpowered input rails. To protect the DSP from long-term
reliability problems, it is recommended to avoid any clock signal to the DSP until the DSP power rail is also
powered up. This can be achieved in two ways using the CDCM6208V1F:
1. Digital control: Initiating a configuration of all registers so that all outputs are disabled, and then turning on
outputs one by one through serial interface after each DSP rail becomes powered up accordingly.
2. Output Power supply domain control: An even easier scheme might be to connect the clock output power
supply VDD_Yx to the corresponding DSP input clock supply domain. In this case, the CDCM6208V1F
output will remain disabled until the DSP rails ramps up as well. Figure 49 shows the turn-on behavior.
Figure 49. Sequencing the Output Turn-on Through Sequencing the Output Supplies. Output Y2 Powers
Up While Output Y0 is Already Running.
66
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: CDCM6208V1F


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn