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CDCM6208V1FRGZR Datasheet(PDF) 65 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 65 Page - Texas Instruments

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PS_A
SYNCN
Y0
Y0
One pre-scaler clock cycle
uncertainty, of when the
output turns on for one
device in one particular
configuration
Outputs tristates
Outputs turned on
Possibility (A)
Possibility (B)
CDCM6208V1F
www.ti.com
SCAS943 – MAY 2015
The fractional divider output jitter is a function of fractional divider input frequency and furthermore depends on
which bits are exercised within the fractional divider. Exercising only MSB or LSB bits provides better jitter than
exercising bits near the center of the fractional divider. Jitter data are provided in this document, and vary from
50 ps-pp to 200 ps-pp, when the device is operated as a frequency synthesizer with high PLL bandwidths
(approximately 100 kHz to 400 kHz). When the device is operated as a jitter cleaner with low PLL bandwidths (<
1 kHz), its additive total jitter increases by as much as 30 ps-pp. The fractional divider can be used in integer
mode. However, if only an integer divide ratio is needed, it is important to disable the corresponding fractional
divider enable bit, which engages the higher performing integer divider.
11.2.1.16.5
Output Synchronization
Both types of output dividers can be synchronized using the SYNCN signal. For the CDCM6208V1F, this signal
comes from the SYNCN pin or the soft SYNCN register bit R3.5. The most common way to execute the output
synchronization is to toggle the SYNCN pin. When SYNC is asserted (VSYNCN ≤ VIL), all outputs are disabled
(high-impedance) and the output dividers are reset. When SYNC is de-asserted (VSYNCN ≥ VIH), the device first
internally latches the signal, then retimes the signal with the pre-scaler, and finally turns all outputs on
simultaneously. The first rising edge of the outputs is therefore approximately 15 ns to 20 ns delayed from the
SYNC pin assertion. For one particular device configuration, the uncertainty of the delay is ±1 PS_A clock cycles.
For one particular device and one particular configuration, the delay uncertainty is one PS_A clock cycle.
The SYNC feature is particularly helpful in systems with multiple CDCM6208V1F. If SYNC is released
simultaneously for all devices, the total remaining output skew uncertainty is ±1 clock cycles for all devices
configured to identical pre-scaler settings. For devices with varying pre-scaler settings, the total part-to-part skew
uncertainty due to sync remains ±2 clock cycles.
Outputs Y0, Y1, Y4, and Y5 are aligned with the PS_A output while outputs Y2, Y3, Y6, and Y7 are aligned with
the PS_B output). All outputs Y[7:0] turn on simultaneously, if PS_B and PS_A are set to identical divide values
(PS_A=PS_B).
Figure 48. SYNCN to Output Delay Uncertainty
Copyright © 2015, Texas Instruments Incorporated
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