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CDCM6208V1FRGZR Datasheet(PDF) 61 Page - Texas Instruments
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CDCM6208V1FRGZR Datasheet(HTML) 61 Page - Texas Instruments
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SCAS943 – MAY 2015
SmartMux input frequency limitation: In the automatic mode, the frequencies of both inputs to the smart mux
(PRI_REF divided by R and SEC_REF) need to be similar; however, they can vary by up to 20%.
Switching behavior: The input clocks can have any phase. When switching happens between one input clock to
the other, the phase of the output clock slowly transitions to the phase of the newly selected input clock. There
will be no-phase jump at the output. The phase transition time to the new reference clock signal depends on the
PLL loop filter bandwidth. Auto-switch assigns higher priority to PRI_REF and lower priority to SEC_REF. The
timing diagram of an auto-switch at the input MUX is shown in Figure 45.
Figure 45. Smart Input MUX Auto-Switch Mode Timing Diagram
126.96.36.199 Universal INPUT Buffer (PRI_REF, SEC_REF)
The universal input buffers support multiple signaling formats (LVDS, CML or LVCMOS) and these require
external termination schemes. The secondary input buffer also supports crystal inputs and Table 28 provides the
characteristics of the crystal that can be used. Both inputs incorporate hysteresis.
188.8.131.52 VCO Calibration
The LC VCO is designed using high-Q monolithic inductors and has low phase noise characteristics. The VCO of
the CDCM6208V1F must be calibrated to ensure that the clock outputs deliver optimal phase noise performance.
Fundamentally, a VCO calibration establishes an optimal operating point within the tuning range of the VCO.
While transparent to the user, the CDCM6208V1F and the host system perform the following steps comprising a
VCO calibration sequence:
1. Normal Operation- When the CDCM6208V1F is in normal (operational) mode, the state of both the power
down pin (PDN) and reset pin (RESETN) is high.
2. Entering the reset state – If the user wishes to restore all device defaults and initiate a VCO calibration
sequence, then the host system must place the device in reset via the PDN pin, via the RESETN pin, or by
removing and restoring device power. Pulling either of these pins low places the device in the reset state.
Holding either pin low holds the device in reset.
3. Exiting the reset state – The device calibrates the VCO either by exiting the device reset state or through
the device reset command initiated via the host interface. Exiting the reset state occurs automatically after
power is applied and/or the system restores the state of the PDN or RESETN pins from the low to high state.
Exiting the reset state using this method causes the device defaults to be loaded/reloaded into the device
register bank. Invoking a device reset via the register bit does not restore device defaults; rather, the device
retains settings related to the current clock frequency plan. Using this method allows for a VCO calibration
for a frequency plan other than the default state (i.e. the device calibrates the VCO based on the settings
contained within the register bank at the time that the register bit is accessed). The nominal state of this bit is
low. Writing this bit to a high state and then returning it to the low state invokes a device reset without
restoring device defaults.
4. Device stabilization – After exiting the reset state as described in Step 3, the device monitors internal
voltages and starts a reset timer. Only after internal voltages are at the correct level and the reset time has
expired will the device initiate a VCO calibration. This ensures that the device power supplies and phase
locked loops have stabilized prior to calibrating the VCO.
5. VCO Calibration – The CDCM6208V1F calibrates the VCO. During the calibration routine, the device holds
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